SK海力士发布CPO路线图，用光连接内存
SK海力士于8月20日宣布，在国际学术期刊《自然·电子学》上发表论文，概述了共封装光学（CPO）技术路线图。该论文题为“Co-packaged o”，展示了将光互连集成到内存芯片封装中的计划，旨在提升数据传输速率并降低功耗。此举表明SK海力士正积极布局下一代内存互连技术，以应对AI和高性能计算对带宽的需求。
原文深度解读
SK海力士于8月20日宣布在国际学术期刊《自然·电子学》上发表论文，概述共封装光学（CPO）技术路线图。论文由SK海力士AI基础设施团队负责人Seunghoon Hong和弗吉尼亚大学电气与计算机工程教授Kyu Sang Lee共同通讯，参与方包括伊利诺伊大学厄巴纳-香槟分校、南洋理工大学、麻省理工学院和延世大学。文章提出CPO作为解决AI计算平台“带宽墙”的方案，设定了下一代AI基础设施CPO的性能目标（每节点带宽>100 Tb/s、能耗<1 pJ/bit、芯片间延迟<10 ns），并规划了从2D封装到2.5D中介层再到3D异构集成的技术路径，以及将光连接扩展到内存接口的“以光为中心”架构。该文与电子元器件供应链相关，涉及内存、光互连、封装技术等关键环节。
- SK海力士于8月20日宣布在《自然·电子学》发表论文，标题为“Co-packaged optics for high-performance computing and artificial intelligence”，将CPO视为AI计算平台“带宽墙”的解决方案。
- 研究由SK海力士AI基础设施团队负责人Seunghoon Hong和弗吉尼亚大学电气与计算机工程教授Kyu Sang Lee共同通讯，参与者包括UIUC、NTU、MIT和延世大学的研究人员。
- 论文定义了下一代AI基础设施CPO的性能目标：每节点带宽超过100 Tb/s，数据传输能耗低于1 pJ/bit，芯片间延迟低于10 ns。
- 技术发展路径从2D封装到2.5D中介层，再到3D异构集成，并提出了商业化挑战。
- 长期方向是“以光为中心”的架构，通过光中介层直接连接内存和处理器，使多个加速器共享内存池，以支持更大模型。
- 硬件计算性能每两年增长约3倍，而互连带宽仅增长1.4倍，造成AI数据中心扩展的瓶颈。
供应链影响
- CPO技术若实现商业化，可能推动光芯片、硅光子引擎、光中介层等新型元器件的需求增长，影响相关供应链布局。
- SK海力士从系统视角开发内存，可能改变内存与光互连组件的集成方式，取决于技术成熟度和成本。
- 3D异构集成和超薄光学材料集成技术可能对封装材料、设备供应商提出新要求，具体影响取决于研发进展。
- CPO性能目标（如>100 Tb/s带宽）可能促使高速光模块、连接器、测试设备等供应链升级，但时间表取决于产业化进程。
- “以光为中心”架构可能推动内存池化相关硬件（如光互连内存模块）的发展，但市场接受度取决于系统级性能提升和成本效益。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
从左至右：SK海力士团队负责人Seunghoon Hong和弗吉尼亚大学教授Kyu Sang Lee。（图片来源：SK海力士）
SK海力士于8月20日宣布，在国际学术期刊《自然·电子学》上发表了一篇概述共封装光学（CPO）技术路线图的论文。
该论文题为“用于高性能计算和人工智能的共封装光学”，将CPO视为人工智能（AI）计算平台面临的“带宽墙”的解决方案，并指明了该技术的发展方向。
这项研究由通讯作者Seunghoon Hong（SK海力士AI基础设施团队负责人）和Kyu Sang Lee（弗吉尼亚大学电气与计算机工程教授）领导。来自伊利诺伊大学厄巴纳-香槟分校（UIUC）、南洋理工大学（NTU）、麻省理工学院（MIT）和延世大学的研究人员也参与了研究。
Hong负责SK海力士AI内存行业的中长期战略。SK海力士最近开始从系统角度而非独立组件角度来对待内存。Lee正在研究异构集成，将超薄光学和电子器件组合在单个封装中，用于下一代计算系统。
CPO性能目标和3D异构集成挑战
解释CPO技术的材料。（来源：SK海力士）
CPO是一种下一代封装技术，将使用光传输信号的光学芯片（即硅光子引擎）与高性能电子芯片集成在单个封装中。“这是一种将光收发器（TRx）和处理器置于同一封装中的技术，使芯片能够使用光而不是长距离电互连来交换数据，”Hong说。
研究人员为下一代AI基础设施CPO定义了性能目标，包括每节点带宽超过100太比特每秒（Tb/s）、数据传输能耗低于1皮焦耳每比特（pJ/bit）、芯片间延迟低于10纳秒（ns）。他们还概述了从二维（2D）封装到2.5维（2.5D）中介层再到三维（3D）异构集成的技术发展路径，以及商业化挑战。
研究人员还提出了CPO的长期方向，将光连接扩展到内存接口。目标是实现一种“以光为中心”的架构，通过光中介层直接连接内存和处理器，克服传统封装的空间限制。这种架构将允许多个加速器共享一个结合了大内存空间的内存池，实现更灵活的系统级数据移动，并更容易容纳日益增大的模型。
以光为中心的架构说明。（来源：SK海力士）
CPO通过光学引擎最小化封装内电信号传输的距离，同时使用光纤承载的光进行更长距离的传输。它可以将通信从芯片扩展到服务器机架和机柜，同时保持高带宽密度、能效、可扩展性和稳定的信号质量。
机架是容纳多个服务器的框架，而机柜将多个机架组合成一个集成网络和电源管理的单元。大规模AI模型在机柜级环境中训练。单个芯片（包括计算设备和内存）之间以及机架之间的数据移动速度和效率决定了整体系统性能。
超越铜互连以解决带宽墙
传统的铜互连随着传输距离的增加，信号失真和衰减更严重。添加补偿电路来纠正这些问题会增加功耗、发热和延迟。
“即使计算芯片性能提高，如果芯片间的数据移动跟不上，整体系统性能也无法提升，”Lee说。“用光代替面临物理限制的铜互连来移动数据，是最有前景的扩展路径。”
高带宽内存（HBM）正在最小化AI加速器封装内的内存瓶颈。然而，随着连接数千个图形处理单元（GPU）和HBM的大规模集群出现，系统级的“带宽墙”已成为新的挑战。
AI硬件计算性能和互连带宽的增长趋势。（来源：SK海力士）
硬件计算性能最近每两年增长约三倍。相比之下，互连带宽仅增长了1.4倍，造成了AI数据中心扩展的瓶颈。
“光互连仍处于工业化的早期阶段，从集成低功耗光学器件到保持数据一致性的信号传输协议和可靠性技术，许多挑战依然存在，”Lee说。“关键是将内存器件、控制器、光学器件和封装作为单一系统进行协同设计，这正是与SK海力士合作的重要意义所在。”
研究人员计划通过超薄光学材料集成技术和基于微型发光二极管（LED）的大规模并行光互连等研究，提出高效的数据传输方法。
From left, SK hynix team leader Seunghoon Hong and UVA Professor Kyu Sang Lee. (Photo: SK hynix)
SK hynix said on Aug. 20 that it published a paper outlining a technology roadmap for co-packaged optics (CPO) in the international academic journal Nature Electronics.
The paper, titled "Co-packaged optics for high-performance computing and artificial intelligence," identifies CPO as a solution to the "bandwidth wall" facing artificial intelligence (AI) computing platforms and lays out a direction for the technology's development.
The research was led by corresponding authors Seunghoon Hong, a team leader responsible for AI infrastructure at SK hynix, and Kyu Sang Lee, a professor of electrical and computer engineering at the University of Virginia (UVA). Researchers from the University of Illinois Urbana-Champaign (UIUC), Nanyang Technological University (NTU), Massachusetts Institute of Technology (MIT) and Yonsei University also participated.
Hong is responsible for SK hynix's mid- to long-term strategy for the AI memory industry. SK hynix has recently been approaching memory from a system perspective rather than as a standalone component. Lee is researching heterogeneous integration that combines ultrathin optical and electronic devices in a single package for next-generation computing systems.
CPO Performance Targets and 3D Heterogeneous Integration Challenges
Material explaining CPO technology. (Source: SK hynix)
CPO is a next-generation packaging technology that integrates optical chips, or silicon photonics engines, that transmit signals using light with high-performance electronic chips in a single package. "It is a technology that places optical transceivers (TRx) and processors in the same package so chips can exchange data using light instead of long electrical interconnects," Hong said.
The researchers defined performance targets for next-generation AI infrastructure CPO, including bandwidth of more than 100 terabits per second (Tb/s) per node, energy consumption of less than 1 picojoule per bit (pJ/bit) for data transmission and chip-to-chip latency of less than 10 nanoseconds (ns). They also outlined a technology development path from two-dimensional (2D) packaging to 2.5-dimensional (2.5D) interposers and three-dimensional (3D) heterogeneous integration, along with commercialization challenges.
The researchers also proposed a long-term direction for CPO that extends optical connectivity to memory interfaces. The goal is an "optics-centric" architecture that overcomes the spatial limitations of conventional packaging by directly connecting memory and processors through an optical interposer. Such an architecture would allow multiple accelerators to share a memory pool combining a large memory space, enabling more flexible system-level data movement and making it easier to accommodate increasingly large models.
Explanation of the optics-centric architecture. (Source: SK hynix)
CPO minimizes the distance traveled by electrical signals within a package through optical engines, while using light carried over optical fiber for longer distances. It can extend communications from chips to server racks and pods while maintaining high bandwidth density, energy efficiency, scalability and stable signal quality.
A rack is a frame that houses multiple servers, while a pod combines multiple racks into a unit with integrated network and power management. Large-scale AI models are trained in pod-scale environments. The speed and efficiency of data movement between individual chips, including computing devices and memory, and between racks determine overall system performance.
Moving Beyond Copper Interconnects to Address the Bandwidth Wall
Conventional copper interconnects suffer greater signal distortion and attenuation as transmission distances increase. Adding compensation circuitry to correct these problems increases power consumption, heat generation and latency.
"Even if computing chip performance improves, overall system performance cannot increase if data movement between chips fails to keep pace," Lee said. "Moving data with light instead of copper interconnects, which face physical limitations, is the most promising path for scaling."
High-bandwidth memory (HBM) is minimizing memory bottlenecks within AI accelerator packages. However, as massive clusters connecting thousands of graphics processing units (GPUs) and HBM emerge, a system-level "bandwidth wall" has become a new challenge.
Growth trends in AI hardware computing performance and interconnect bandwidth. (Source: SK hynix)
Hardware computing performance has recently increased about threefold every two years. Interconnect bandwidth, by contrast, has increased by 1.4 times, creating a bottleneck for AI data center expansion.
"Optical interconnects are still at an early stage of industrialization, with many challenges remaining, ranging from integrating low-power optical devices to signal transmission protocols that maintain data consistency and reliability technologies," Lee said. "The key is to co-design memory devices, controllers, optical devices and packages as a single system, and that is where collaboration with SK hynix has significant meaning."
The researchers plan to propose high-efficiency data transmission approaches through research including ultrathin optical material integration technology and massively parallel optical interconnects based on micro light-emitting diodes (LEDs).