SK海力士与闪迪发布首个HBF标准，支持高达512GB容量
8月4日，SK海力士与闪迪联合发布了业界首个高带宽闪存（HBF）标准规范，该技术旨在提供高容量与高带宽，支持最高512GB容量。此标准为下一代存储器技术奠定基础，与元器件供应链中存储产品的演进相关。
原文深度解读
SK海力士与闪迪于8月4日联合发布了业界首个高带宽闪存（HBF）标准规范，该技术基于NAND闪存，旨在为AI应用提供高容量和高带宽，支持最高512GB容量和0.4至3TB/s的带宽。该标准通过开放计算项目（OCP）发布，并采用UCIe接口。SK海力士在FMS 2026上展示了HBF及第10代375层4D NAND技术，计划明年年初量产基于该技术的企业级SSD。该事件与电子元器件供应链中存储产品的技术演进和生态发展相关。
- SK海力士与闪迪于8月4日发布了业界首个高带宽闪存（HBF）标准规范，该规范通过开放计算项目（OCP）发布。
- HBF是一种基于NAND的存储架构，垂直堆叠NAND die，类似于HBM，但提供更高的容量扩展性和高带宽性能，适用于AI推理工作负载。
- 初始规范定义了8层和16层NAND die堆叠两种配置，容量最高512GB，带宽分为三个性能等级，范围从0.4TB/s到3TB/s。
- HBF标准采用UCIe接口，允许与不同供应商的CPU和GPU灵活集成。
- HBF联盟成立于2月，成员包括SK海力士、闪迪、谷歌和Tenstorrent。
- SK海力士在FMS 2026上展示了第10代375层4D NAND，与前代相比，每瓦性能提升2.5倍，计划明年年初量产基于该技术的企业级SSD。
供应链影响
- HBF标准的发布可能推动AI存储生态系统的形成，影响存储设备供应商和处理器制造商之间的合作模式，具体取决于生态系统的成熟度。
- HBF采用UCIe接口可能促进chiplet互连技术的标准化，从而影响相关IP和封装供应链的需求，取决于市场接受度。
- SK海力士计划量产375层4D NAND，可能影响企业级SSD的供应和性能竞争格局，具体取决于量产进度和良率。
- HBF的高容量和高带宽特性可能改变AI推理服务器的存储架构，进而影响内存和存储产品的需求结构，取决于AI工作负载的演进。
- HBF联盟的开放合作模式可能吸引更多参与者，影响存储技术专利和标准制定的话语权，取决于联盟的扩展情况。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
SK海力士发布了业界首个高带宽闪存（HBF）标准规范。（图片来源：SK海力士）
SK海力士与闪迪于8月4日联合发布了业界首个高带宽闪存（HBF）标准规范，这是一种下一代存储技术，旨在为人工智能应用提供高容量和高带宽。
该公告发布距HBF标准规范联盟成立已有六个月，该联盟于2月成立，两家公司均参与其中。该规范通过开放计算项目（OCP）发布，OCP是全球最大的开源数据中心技术联盟。
HBF是一种基于NAND的存储架构，垂直堆叠NAND die，类似于高带宽内存（HBM）采用的方法，以提高数据传输速度。与基于DRAM的HBM不同，HBF在保持高带宽性能的同时，在容量上具有更大的可扩展性，使其成为需要大存储容量和快速数据访问的AI推理工作负载的有前景的解决方案。
初始规范定义了使用8层和16层NAND die堆叠的两种配置。存储容量最高可达512GB，而带宽分为三个性能等级，范围从0.4太字节每秒（TB/s）到3TB/s。
在芯片连接方面，该标准采用通用小芯片互连标准（UCIe），这是一种行业标准的开放接口，可实现小芯片之间的高速通信。UCIe的使用使HBF设备能够灵活地与不同供应商的CPU和GPU等处理器集成。
该规范还包括HBF die堆叠的接口定义、电气特性、可靠性和封装指南，以及数据输入输出操作的软件建议。
SK海力士表示，计划加速HBF在新兴AI存储市场中的生态系统发展和更广泛采用。HBF联盟的当前成员包括谷歌和Tenstorrent。公司预计开放合作模式将提高技术成熟度和市场接受度。
SK海力士在FMS 2026上重点展示HBF和375层4D NAND
SK海力士在FMS 2026上展示HBF和其他下一代存储技术。（图片来源：SK海力士）
SK海力士正在参加于8月4日至6日在加利福尼亚举行的未来内存与存储（FMS）2026，并在会上展示HBF技术及其第10代（V10）375层4D NAND。
在活动开幕当天，SK海力士解决方案开发负责人Kim Chun-seon和下一代产品规划负责人Kang Wook-sung将发表联合主题演讲，题为“基于分层内存在智能体AI时代高效实现AI基础设施”。演讲者将讨论基于分层内存系统的下一代架构的需求，并概述未来发展方向。
分层内存是指通过将具有不同特性的多种内存技术集成到统一层次结构中来优化性能的架构。随着智能体AI应用的广泛部署，数据量和性能要求持续上升，传统的单一内存架构日益不足。
8月6日，SK海力士解决方案AT负责人Lim Eui-cheol、闪迪执行副总裁Rajiv Nagavivara以及谷歌DeepMind研究员Xiaoyu Ma将参加题为“用HBF打破内存墙”的小组讨论。该会议将审视AI内存架构中发生的根本性变化，并探讨HBF作为内存瓶颈的潜在解决方案。
公司还设有展览展位，展示合作伙伴关系、下一代存储技术和技术会议。亮点之一是首次公开展示其正在开发的基于V10 375层4D NAND的晶圆和产品。
SK海力士的4D NAND架构结合了Peri Under Cell（PUC）技术（将外围电路置于存储单元阵列下方）和电荷捕获闪存（CTF）技术（将电荷存储在氮化硅等绝缘材料中）。
与前代产品相比，375层4D NAND每瓦性能提升2.5倍。该技术针对数据中心等AI基础设施环境进行了优化，在这些环境中性能和能效都至关重要。SK海力士计划于明年年初开始量产基于新NAND技术的高容量、高性能企业级固态硬盘（eSSD）。
展览还展示了面向移动设备、PC、汽车应用和机器人的产品，以及公司AI内存技术和客户合作成果的演示。
“AI的快速扩张正在推动数据处理架构的根本性重新设计，”Kim表示。“通过HBF，我们旨在扩展内存与存储之间的边界，并为开发提高整体系统效率的新架构做出贡献。”
SK hynix unveiled the industry's first standard specification for High Bandwidth Flash (HBF). (Photo: SK hynix)
SK hynix and Sandisk on Aug. 4 unveiled the industry's first standard specification for High Bandwidth Flash (HBF), a next-generation memory technology designed to deliver both high capacity and high bandwidth for artificial intelligence applications.
The announcement comes six months after the launch of the HBF Specification Standardization Consortium, established in February with participation from both companies. The specification was presented through the Open Compute Project (OCP), the world's largest open-source data center technology consortium.
HBF is a NAND-based memory architecture that vertically stacks NAND dies, similar to the approach used in High Bandwidth Memory (HBM), to increase data transfer speeds. Unlike DRAM-based HBM, HBF offers greater scalability in capacity while maintaining high-bandwidth performance, making it a promising solution for AI inference workloads that require both large memory capacity and fast data access.
The initial specification defines two configurations using eight-layer and 16-layer NAND die stacks. Memory capacity scales up to 512GB, while bandwidth is classified into three performance tiers ranging from 0.4 terabytes per second (TB/s) to 3TB/s.
For chip connectivity, the standard adopts Universal Chiplet Interconnect Express (UCIe), an industry-standard open interface that enables high-speed communication between chiplets. The use of UCIe allows HBF devices to be flexibly integrated with processors such as CPUs and GPUs from different vendors.
The specification also includes interface definitions, electrical characteristics, reliability and packaging guidelines for HBF die stacks, and software recommendations for data input and output operations.
SK hynix said it plans to accelerate ecosystem development and broader adoption of HBF in the emerging AI storage market. Current members of the HBF consortium include Google and Tenstorrent. The company expects the open collaboration model to improve both technical maturity and market acceptance.
SK hynix Highlights HBF and 375-Layer 4D NAND at FMS 2026
SK hynix is showcasing HBF and other next-generation memory technologies at FMS 2026. (Photo: SK hynix)
SK hynix is participating in Future of Memory and Storage (FMS) 2026, being held in California from Aug. 4 to Aug. 6, where it is showcasing HBF technology and its 10th-generation (V10) 375-layer 4D NAND.
On the opening day of the event, Kim Chun-seon, head of Solution Development at SK hynix, and Kang Wook-sung, head of Next-Generation Product Planning, are delivering a joint keynote presentation titled "Efficient Implementation of AI Infrastructure Based on Tiered Memory in the Agentic AI Era." The speakers will discuss the need for next-generation architectures built on tiered memory systems and outline future development directions.
Tiered memory refers to an architecture that optimizes performance by integrating multiple memory technologies with different characteristics into a unified hierarchy. As agentic AI applications become more widely deployed, data volumes and performance requirements continue to rise, making traditional single-memory architectures increasingly inadequate.
On Aug. 6, Lim Eui-cheol, head of Solution AT at SK hynix, Rajiv Nagavivara, executive vice president at Sandisk, and Xiaoyu Ma, a researcher at Google DeepMind, will participate in a panel discussion titled "Breaking the Memory Wall with HBF." The session will examine fundamental changes occurring in AI memory architectures and explore HBF as a potential solution to memory bottlenecks.
The company is also operating an exhibition booth featuring partnership displays, next-generation memory technologies and technical sessions. Among the highlights is the first public display of wafers and products based on its V10 375-layer 4D NAND currently under development.
SK hynix's 4D NAND architecture combines Peri Under Cell (PUC), which places peripheral circuitry beneath the memory cell array, with Charged Trap Flash (CTF) technology that stores charge in insulating materials such as silicon nitride.
Compared with the previous generation, the 375-layer 4D NAND delivers 2.5 times higher performance per watt. The technology is optimized for AI infrastructure environments such as data centers, where both performance and energy efficiency are critical. SK hynix plans to begin mass production of high-capacity, high-performance enterprise solid-state drives (eSSDs) based on the new NAND technology early next year.
The exhibition also features products targeting mobile devices, PCs, automotive applications and robotics, along with demonstrations of the company's AI memory technologies and customer collaboration achievements.
"The rapid expansion of AI is driving a fundamental redesign of data processing architectures," Kim said. "Through HBF, we aim to extend the boundary between memory and storage and contribute to the development of new architectures that improve overall system efficiency."