分析师称台积电HBM封装良率问题利好英特尔
台积电CoWoS封装产能瓶颈及HBM封装良率问题，可能为英特尔代工业务带来机遇。AI芯片制造商正关注英特尔的EMIB封装技术和新型存储技术。
原文深度解读
本文基于Counterpoint Research联合创始人Neil Shah及其他分析师对EE Times的评论，探讨台积电在HBM封装（CoWoS）方面的良率与产能瓶颈如何为英特尔代工业务带来机遇。文章涉及台积电、英特尔、英伟达、AMD、博通、谷歌、联发科、苹果等公司，时间点为2026年8月。关键数字包括：台积电CoWoS封装中HBM堆叠数量（8个或更多）、英特尔EMIB在Sapphire Rapids和Ponte Vecchio中的量产应用、谷歌TPUv9t系列采用EMIB-T、特朗普政府持有英特尔10%股份等。文章与电子元器件供应链直接相关，聚焦先进封装技术（CoWoS、EMIB、ZAM、XBM）对AI芯片制造和代工竞争格局的影响。
- 台积电的CoWoS先进封装技术是英伟达、AMD和博通等AI客户多年来的主流选择，但已成为生产瓶颈。
- HBM依赖台积电CoWoS硅中介层，带来厚封装、良率风险、产能限制和高报废成本，为替代方案创造机会。
- 英特尔EMIB封装已量产，长期方案包括Z-angle memory (ZAM)和cross-batch memory (XBM)，可消除中介层问题。
- 大型硅芯片缺陷率高，若中介层在最终封装时失效，GPU芯片和所有8个或更多HBM堆叠都会报废，造成数千美元损失。
- Counterpoint渠道检查显示，谷歌和AI ASIC设计伙伴联发科将使用英特尔代工的EMIB-T用于谷歌即将推出的TPUv9t (Humufish)、TPUv9t+ (Triggerfish)及后续产品。
- 台积电和HBM仍是同时训练和推理的最安全、最灵活的通用平台，英伟达和AMD尚未表现出多元化意愿，但谷歌（与联发科合作）正在寻求多元化。
供应链影响
- 台积电CoWoS产能瓶颈可能促使部分AI芯片客户（如谷歌）转向英特尔代工，从而改变先进封装供应链的竞争格局。
- 英特尔EMIB、ZAM和XBM等封装技术的量产进度和客户采用情况，可能影响其对台积电的替代能力，取决于技术成熟度和良率表现。
- HBM封装良率问题可能导致AI芯片成本上升，进而影响相关芯片和系统的定价，但具体影响取决于台积电和英特尔的良率改善情况。
- 英特尔代工业务的增长可能取决于谷歌、联发科以及一级存储厂商的支持，这些合作可能带动相关供应链（如存储、封装材料）的需求变化。
- 台积电CoWoS-L与英特尔EMIB在架构上的相似性可能加剧技术竞争，但台积电的良率优势（如分析师Mike Demler所述）可能维持其市场地位，具体取决于未来产能扩张和良率表现。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
台积电的HBM封装良率问题为英特尔带来机遇，分析师称
根据Counterpoint Research联合创始人Neil Shah及其他分析师对EE Times的评论，台积电在将AI加速器与高带宽内存（HBM）集成到单个芯片上的困难，为英特尔赢得代工客户提供了机会。
Shah在8月17日提供给EE Times的一份报告中表示，台积电的CoWoS先进封装技术多年来一直是英伟达、AMD和博通等AI客户的中流砥柱，但已成为生产瓶颈。
“HBM对台积电CoWoS硅中介层的依赖带来了高昂的成本，包括厚封装、良率风险、产能限制和高报废成本，从而为可信的替代方案创造了机会，”Shah说。英特尔已量产的EMIB先进封装，以及其长期解决方案如Z-angle内存（ZAM）和cross-batch内存（XBM），可以帮助AI芯片制造商消除台积电的中介层问题，Shah补充道。
“大型硅芯片具有高缺陷率。如果中介层在最终封装时失效，GPU芯片和所有八个或更多附着的HBM堆叠都会报废，”Shah说。“由于互连或中介层缺陷而报废已组装封装，会在最后一步毁掉价值数千美元的硅。”
由Hynetek Semiconductor Co., Ltd. 2026年8月24日
由Juan Rey，西门子EDA Calibre部门高级副总裁、总经理兼首席技术官 2026年8月24日
由Arduino团队 2026年8月19日
（来源：Counterpoint，Intel）
构建实力
其他分析师也认为英特尔正在增强实力。
“英特尔已经拥有许多重要的外部封装客户，未来几年增长潜力良好，”International Business Strategies首席执行官Handel Jones告诉EE Times。“英特尔在封装方面拥有良好的技术，并且正在扩大产能，包括在新墨西哥州圣塔菲。”
Jones以与客户的保密协议为由，拒绝透露英特尔代工客户的身份。
Shah表示，英特尔的EMIB已在Sapphire Rapids和Ponte Vecchio处理器以及定制加速器设计等大批量产品中得到验证。
Counterpoint表示，其渠道检查表明，谷歌和AI ASIC设计合作伙伴联发科将使用英特尔代工的EMIB-T用于谷歌即将推出的TPUv9t（Humufish）、TPUv9t+（Triggerfish）及后续产品。
英特尔仍面临障碍，Counterpoint表示。
“台积电和HBM仍然是同时训练和推理的最安全、最灵活的通用平台，”Shah说。“英伟达和AMD迄今未表现出多元化意愿。与此同时，我们看到谷歌（与联发科合作）正在寻求多元化，这将意义重大，因为谷歌是全球第二大加速器公司。”
5月，《华尔街日报》报道称，苹果可能向英特尔订购芯片，这笔交易由美国总统唐纳德·特朗普促成。特朗普政府去年持有英特尔10%的股份。
封装
先进封装通过将多个芯片和芯粒集成到日益密集的封装中，延续了摩尔定律的优势。英伟达最新的AI芯片在单个封装中集成了两个计算芯片上的数千亿个晶体管。
从性能和功耗的角度来看，封装技术的改进将比台积电和英特尔等领先代工厂从2.0纳米向1.4纳米工艺迁移更为重要，Jones表示。
英特尔的机会取决于及时执行以及谷歌和联发科等公司以及一级存储厂商的支持，Counterpoint表示。
据该研究公司称，英特尔的EMIB以及ZAM和XBM将成为这一转变背后的因素。
2月，英特尔和软银子公司Saimemory宣布了ZAM，一种堆叠DRAM技术。ZAM将作为HBM的节能替代方案。长期来看，XBM将使用后端（BEOL）薄膜晶体管和串行UCIe链路来消除中介层。
英特尔首席执行官Lip-Bu Tan最近暗示了内存对公司日益增长的重要性。
保持竞争力
Counterpoint表示，台积电正在增强CoWoS以保持竞争力。
Counterpoint报告指出，CoWoS-L在架构上与EMIB相似，使用小型局部硅桥进行高密度芯片间布线。英特尔将EMIB桥直接嵌入有机基板腔体内，而台积电将集成桥嵌入硅晶圆层中的中间再分布层（RDL），然后将其连接到基板，报告称。
“我倾向于相信台积电的CoWoS工艺具有出色的良率，”分析师Mike Demler告诉EE Times。“较新的CoWoS-L可能早期存在一些良率问题，并且有报道称英伟达的Vera Rubin出现延迟，但我不知道目前有任何良率问题。”
Demler表示，英特尔从台积电手中夺取AI芯片客户的机会看起来不错。
“EMIB消除了中介层，而Foveros（英特尔的3D芯片堆叠技术）提供了台积电不具备的芯片堆叠和其他功能，”他说。“至少，英特尔有机会因为台积电的产能短缺而获得客户。”
台积电和英特尔在本文发表前未回应EE Times的置评请求。
另请阅读：
IBM、Synopsys通过热建模技术迈向1.4纳米节点
分析师称台积电将难以满足AI需求多年
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AI与大数据、芯粒、HBM、SoC
英特尔、英特尔代工、台积电
TSMC’s difficulty stitching together AI accelerators with high-bandwidth memory (HBM) on a single chip gives Intel a chance to win foundry customers, according to Counterpoint Research co-founder Neil Shah and other analysts commenting to EE Times.
TSMC’s CoWoS advanced packaging tech, which has been a mainstay for AI customers like Nvidia, AMD, and Broadcom for years, has become a production bottleneck, Shah said in an Aug. 17 report he provided to EE Times.
“HBM’s reliance on TSMC’s CoWoS silicon interposers carries steep costs with thick packages, yield risk, capacity constraints and high scrap costs, thus creating an opening for credible alternatives,” Shah said. Intel’s EMIB advanced packaging that’s in production, as well as the company’s longer-term solutions like Z-angle memory (ZAM) and cross-batch memory (XBM), can help eliminate TSMC’s interposer problem for AI chipmakers, Shah added.
“Large silicon dies have high defect rates. If the interposer fails during final packaging, the GPU die and all eight or more attached HBM stacks are ruined,” Shah said. “Scrapping an assembled package because of an interconnect or interposer defect destroys thousands of dollars in silicon at the final step.”
By Hynetek Semiconductor Co., Ltd. 08.24.2026
By Juan Rey, Senior Vice President, General Manager and CTO of the Calibre segment, Siemens EDA 08.24.2026
By Arduino Team 08.19.2026
(Sources: Counterpoint, Intel)
Building strength
Other analysts agreed that Intel is building strength.
“Intel already has a number of important external customers for packaging with good growth potential over the next few years,” International Business Strategies CEO Handel Jones told EE Times. “Intel has good technology in packaging and is expanding capacity including in Santa Fe, New Mexico.”
Jones declined to identify Intel Foundry customers, citing confidentiality agreements with clients.
Intel’s EMIB is proven in high-volume products like the company’s Sapphire Rapids and Ponte Vecchio processors, as well as custom accelerator designs, Shah said.
Counterpoint said its channel checks suggest Google and AI ASIC design partner MediaTek will use Intel Foundry’s EMIB-T for Google’s upcoming TPUv9t (Humufish), TPUv9t+ (Triggerfish), and beyond.
Intel still faces hurdles, according to Counterpoint.
“TSMC and HBM remains the safest, most flexible generalist platform for simultaneous training
and inference,” Shah said. “Nvidia and AMD have so far showed no inclination to diversify. At the same time, we see Google [with MediaTek] looking to diversify, which would be huge as it [Google] is the second largest accelerator company in the world.”
In May, the Wall Street Journal reported that Apple may order chips from Intel, a deal prompted by U.S. President Donald Trump. The Trump administration took a 10% stake in Intel last year.
Packaging
Advanced packaging has extended the benefits of Moore’s Law by allowing multiple dies and chiplets to be integrated into increasingly dense packages. Nvidia’s latest AI chips integrate hundreds of billions of transistors across two compute dies in a single package.
From a performance and power-consumption perspective, enhancements in packaging tech will be more important than the migration of leading foundries like TSMC and Intel from 2.0-nm to 1.4-nm chip processes, Jones said.
Intel’s chance depends on timely execution and support from companies like Google and MediaTek as well as Tier-1 memory players, Counterpoint said.
Intel’s EMIB, together with ZAM and XBM, will be factors behind the transition, according to the research firm.
In February, Intel and SoftBank subsidiary Saimemory announced ZAM, a stacked DRAM technology. ZAM would serve as an energy-efficient alternative to HBM. In the longer term, XBM would use back-end-of-line (BEOL) thin-film transistors and serial UCIe links to eliminate interposers.
Intel CEO Lip-Bu Tan recently telegraphed memory’s increasing importance to the company.
Staying competitive
TSMC is enhancing CoWoS to stay competitive, Counterpoint said.
CoWoS-L is architecturally similar to EMIB, using small, localized silicon bridges for high-density die-to-die routing, the Counterpoint report noted. Intel embeds an EMIB bridge directly inside an organic substrate cavity while TSMC embeds the integration bridge into an intermediate redistribution layer (RDL) in a silicon wafer layer before attaching it to a substrate, the report said.
“I’m inclined to believe TSMC has excellent yields for its CoWoS processes,” analyst Mike Demler told EE Times. “The newer CoWos-L may have had some early yield issues, and there were reports of some delays with [Nvidia’s] Vera Rubin, but I’m not aware of any current yield issues.”
Intel’s chance to take AI chip customers away from TSMC looks good, Demler said.
“EMIB eliminates the interposer, and Foveros [Intel’s 3D chip-stacking tech] offers die-stacking and other features TSMC doesn’t have,” he said. “If nothing else, Intel has an opportunity to pick up customers because of TSMC’s capacity shortage.”
TSMC and Intel didn’t respond to EE Times before publication of this article.
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AI AND BIG DATA, CHIPLETS, HBM, SOC
INTEL, INTEL FOUNDRY, TSMC