台积电不断演进的设计生态系统内幕：用AI塑造AI的未来
台积电发布开放创新平台生态系统的最新进展，并阐述其愿景：利用台积电AI设计套件实现AI驱动的代理式工作流。该消息涉及台积电及其设计生态伙伴，属于芯片设计与制造环节的生态更新，与元器件供应链的关联在于设计工具与平台能力影响后续芯片设计与流片节奏。
原文深度解读
本文是台积电生态系统与联盟管理总监 Aveek Sarkar 于 2026 年 9 月 24 日发表的访谈，主题为台积电开放创新平台（OIP）生态系统的演进，以及新推出的台积电 AI 设计套件（ADK）如何支持 AI 驱动的代理式工作流。文章涉及台积电及其 90 多家成员、六大联盟、EDA 合作伙伴、IP 联盟伙伴、SK 海力士、三星存储、美光、Ambiq、博通等主体，并提及 100,000+ IP、数字设计生产力提升 3 至 5 倍、模拟/射频设计生产力提升最高 6 倍、OIP 成立 18 年、HBM5 CoWoS 验证等关键数字。与电子元器件供应链的关联在于：设计工具与平台能力、先进制程与封装、HBM 验证及系统级设计支持，可能影响后续芯片设计、流片节奏以及存储与先进封装环节的协同。
- 台积电 OIP 生态系统拥有 90 多家成员、六大联盟和 100,000+ IP，其目标被描述为简化客户设计流程、加速进度并降低流片与营收风险。
- 台积电推出 AI 设计套件（ADK），用于支持基于代理式 AI 的设计工具与流程，并称可将数字设计生产力提升 3 至 5 倍，模拟/射频设计生产力提升最高 6 倍。
- 台积电从计算、集成（与存储）和连接三个角度应对能效挑战，涉及 DTCO、TSMC-SoIC、COUPE 等技术，并强调热、应力、电磁等多物理效应需要生态协作建模。
- 在边缘应用方面，原文称客户趋势明确走向 FinFET 节点，台积电超低漏电 SRAM 可支持极低待机功耗场景；IP 联盟伙伴与客户 Ambiq 在 N12e 工艺上合作实现定制 IP 方案并显著节省漏电功耗。
- OIP 成立 18 年，今年与 SK 海力士、三星存储、美光合作验证 HBM5 CoWoS，各方围绕热-机械应力挑战对齐 DTCO；博通在 NA OIP 论坛展示利用台积电先进技术构建定制 XPU 平台。
- 展望未来，原文提到代理式 AI 可用于根因分析等单一步骤并开始尝试编排流程，客户需要快速获得时序、寄生和热方面的设计决策反馈；台积电还在构建系统级关注能力，覆盖数据中心、人形机器人和 IoT 系统视角。
供应链影响
- 若 ADK 所宣称的设计生产力提升在实际客户流程中兑现，芯片设计周期可能缩短，进而可能影响后续流片节奏与先进制程产能需求的时间分布。
- OIP 对系统级、机架级和 ODM 生态的扩展，可能使电子元器件供应链的协同范围从芯片与先进封装向系统集成环节延伸，但实际影响取决于客户采用速度。
- HBM5 CoWoS 验证涉及 SK 海力士、三星存储和美光，可能强化先进封装与 HBM 存储供应之间的技术协同要求，但量产与供应格局取决于后续验证和客户导入进展。
- 边缘芯片向 FinFET 节点迁移以及超低漏电 SRAM 的应用，可能影响边缘 AI 设备中存储容量与功耗设计取向，但具体元器件需求取决于终端应用放量情况。
- 代理式 AI 工作流对快速反馈和硬件加速的需求，可能带动 EDA、IP 与设计服务环节的工具与流程更新，但供应链影响取决于生态伙伴工具就绪度和客户实际部署。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
作者：Aveek Sarkar，台积电生态系统与联盟管理部总监
2026.09.24
0
台积电推出 AI 设计套件，以赋能 AI 驱动工作流的未来
在这次对话中，台积电生态系统与联盟管理总监 Aveek Sarkar 分享了该晶圆代工厂开放创新平台（OIP）生态系统的最新进展，包括台积电利用新的台积电 AI 设计套件（ADK）赋能 AI 驱动代理式工作流的愿景。
是什么促使台积电决定创建开放创新平台（OIP）生态系统？它如今如何演变为对推动 AI 扩张至关重要的“领导力生态系统”？
随着台积电建立纯晶圆代工模式，OIP 生态系统使硅创新侧实现了民主化。
我们的目标非常简单——如何简化客户设计流程，如何加速他们的进度，以及如何降低他们所做一切的风险，以实现成功流片并取得营收？这是我们六大联盟 90 多家成员共同完全一致的任务。
作者：Aveek Sarkar，台积电生态系统与联盟管理部总监 2026.09.24
作者：Skyeast International Group Limited 2026.09.24
作者：Global Unichip Corp. (GUC) 2026.09.22
当你看我们的 100,000+ IP 和参考流程时，将其描述为领导力生态系统是非常贴切的。但领导力不仅仅在于今天做事。它在于环顾四周，思考我们需要做什么来预先满足客户的需求。
这就是为什么我们通过在新兴设计解决方案上支持客户，并在我们的 OIP 活动上分享。我们有六家初创公司正在从事基于 AI 的 EDA 或通过其 IP 赋能 AI，它们将加入我们。我们正在扩大支持，以使整个代理式 AI 基础设施快速演进。
我们还有一个新的系统级关注点，超越芯片和先进封装，聚焦于机架级，以帮助那些可能严格来说不在我们 OIP 生态系统内、但处于我们客户生态系统内的 ODM。我们希望帮助他们，并让我们的生态系统支持他们。
这就是我们演进的方式。但如果没有 OIP 合作伙伴的承诺，这一切都不可能实现，我们对他们为我们和客户所做的一切深表感谢。
台积电开放创新平台®（OIP）演进里程碑（来源：台积电）
能效可以说是当今 AI 扩张面临的最大挑战。台积电如何与 OIP 合作伙伴合作，利用台积电的先进制程、封装和 COUPE 技术来满足 AI 基础设施巨大的性能和功耗需求？
我认为有一点我们都能完全同意——我们都需要能效！
我们从三个角度看待它：计算、集成（与存储）和连接。
对于计算，我们有 DTCO [设计技术协同优化]，这是台积电同步开发电路级 IP 和工艺技术的方法，以充分释放功耗、性能和面积（PPA）优势的潜力。
但不仅仅是 DTCO。DTCO 让技术准备就绪，但客户应该能够使用它，这就是我们的生态系统介入的地方。我们与合作伙伴合作，使这些流程可用，然后有效地部署给客户，并在整个过程中支持他们。我们的设计服务和价值链联盟实现了这一点。
除了数字计算，我们还关注模拟，特别是因为 I/O 电路对能耗如此关键。我们从 PDK 开发的早期阶段就与合作伙伴合作，以便他们能给我们反馈，从而优化模拟 PPA。
在系统层面，我们有 TSMC-SoIC [系统集成芯片，台积电的 3D 小芯片堆叠技术]，但我们需要确保解决所有相关的多物理效应——热、应力。这就是与生态系统合作真正关键的地方，因为我们可以创建解决方案，但客户必须用它来设计。
对于连接，台积电 COUPE 是一项改变游戏规则的技术，但你必须同时优化电气和光学组件。最高保真度的电磁提取至关重要，而热对性能有很大影响。我们也必须对此建模。当然，不仅仅是这三个领域。我们开始思考系统：封装中的芯片及其连接，但在机架或 IoT 平台中——我们如何解决设计挑战？我们正在扩大生态系统内的关注点来实现这一点。
AI 在设计工具本身中的采用进展如何？台积电如何与 EDA 合作伙伴合作，将 AI 集成到设计工作流中以提高生产力？
我们正在推出台积电 AI 设计套件（ADK），通过支持基于台积电技术特定学习的代理式 AI 设计工具和流程来加速上市时间。这一举措将数字设计生产力提升 3 至 5 倍，模拟/射频设计生产力提升最高 6 倍。
今天，尽管我们的参考流程使客户能够取得显著成果，但他们通常仍需要根据其独特需求进行手动调优和工作流优化。展望未来，我们期望代理式框架加速这些电路和架构特定的优化。与具有静态条件的参考流程不同，台积电 ADK 为代理式框架提供技术知识层，使其能够快速优化调优并满足设计特定目标。虽然我们期望在与客户接触中学到很多，但拥有这个框架将使我们能够非常快速地推动进展。
我们对代理式框架感到非常兴奋，因为其具有自学习、自校正流程的机会。但这段 AI 之旅对我们来说并不新鲜——几年前我们就开始在电路优化和设计空间探索中使用强化学习。我们与合作伙伴合作，确保他们的工具准备就绪。
例如——对于模拟，我们有一种方法可以帮助设计在工艺节点之间迁移。生成式 AI 开辟了新的可能性，但有了代理式 AI，可能性更大。我们将与合作伙伴在台积电 ADK 上合作，我们相信这将是使我们能够支持这一构建的框架。
台积电对 AI 驱动设计流程的愿景（来源：台积电）
随着 AI 工作负载从超大规模数据中心扩展到边缘计算，台积电的设计解决方案如何应对边缘与云端的能效要求？
任何大规模部署的系统都会关注性能、能耗和成本，但在边缘，核心是能耗和成本。越来越清楚的是，客户趋势 [对于边缘芯片] 非常明确地走向 FinFET 节点，以利用能耗优势。我们的超低漏电 SRAM 允许极低待机功耗场景，因此你可以增加更多存储，或者降低电压，从而实现显著的动态功耗降低。
FinFET 在边缘应用中的 CAGR 稳步增长（来源：台积电）
从生态系统的角度来看，我们正在与合作伙伴合作，确保客户能够获得他们需要的 IP，这些 IP 针对其应用及其功耗和成本包络进行了调优。
例如，我们的一个 IP 联盟合作伙伴与我们的客户 Ambiq 合作，在台积电 N12e 工艺上实现定制 IP 解决方案。通过这次合作，他们实现了显著的漏电功耗节省，赋能了 Ambiq 的边缘 AI 应用。
这种生态系统合作如何为客户带来切实的现实成功？您能否分享一个最近的例子，说明 OIP 合作解决了特别复杂的性能或能效挑战？
我们与 OIP 生态系统合作伙伴的合作从第一天起就是我们的核心。自正式成立以来的 18 年里，OIP 生态系统已成为赋能客户创新的驱动力——从行业领导者到新兴初创公司。
作为今年 NA OIP 论坛上我们的客户主题演讲嘉宾，博通 ASIC 产品部门工程副总裁 Greg Dix 展示了他们如何利用台积电的领先技术——在我们强大的设计生态系统的支持下——大规模构建其最新的定制 XPU 平台。他的演讲强调了他们在先进节点采用、异构多芯片集成和近存储协同设计方面的成功。博通是众多与我们合作开创性 AI 硅片的先驱之一，正是我们设计生态系统合作伙伴的集体力量使这些成功成为可能。
每天，都有与各方合作伙伴一起进行的工作，帮助客户应对前所未有的性能和能效设计挑战，尤其是在 AI 迅速崛起的背景下。例如，今年我们与 SK 海力士、三星存储和美光合作验证 HBM5 CoWoS [基板上晶圆上芯片]。这是一个联合项目，每个合作伙伴都在研究最佳实践，围绕热-机械应力挑战对齐 DTCO。
台积电先进节点赋能工作负载特定架构（来源：台积电）
我们还与合作伙伴，特别是我们的 EDA 合作伙伴合作，创建参考方法和最佳实践，我们将通过 AI 设计套件加速这些。这对客户至关重要，因为它减少了他们经历的摩擦，并降低了他们寻求的 PPA 的门槛。今年我们与三大 EDA 供应商合作，为设计服务社区组织高级培训，以提升他们的专业知识，这有助于我们的客户降低风险并更快达到目标。我们已经看到了切实的成果。
另一个例子是 COUPE，系统的电气和光学部分必须在紧凑的外形尺寸内协同优化。我们还需要关注热特性和电磁干扰，必须仔细建模。一些合作伙伴和客户将在今年的 OIP 生态系统论坛活动上就此主题发表论文。
展望未来，OIP 生态系统的下一步是什么？在 AI 时代加速的步伐中，台积电及其合作伙伴将如何继续合作以实现客户设计成功？
每一次技术转型都带来新的挑战，但也带来新的机遇。
人们正在将代理式 AI 用于单个步骤（如根因分析），并开始尝试编排流程，其中多个代理在设计周期中相互协作并共享信息。但我们的客户很快意识到，他们需要快速获得设计决策在时序、寄生或热方面影响的反馈。代理工作更快，它们可以整夜工作，因此可以大幅缩短这些反馈循环。这为围绕下一代引擎的创新开辟了机会，利用硬件加速来支持代理式工作流所需的快速周转时间。还有机会使用定制 LLM 来预测设计权衡选择。
客户问我们是否研究过这一点以及我们如何赋能它。因此，我们未来必须做的事情将需要广泛得多，尤其是在 AI 设计赋能方面，我们才刚刚开始触及表面。
第二件事是我们的系统级关注，这是我们正在构建的新肌肉。显然，我们在芯片和封装方面拥有深厚的专业知识，但我们如何从数据中心、人形机器人或 IoT 系统的角度来看待它？系统是我们正在非常积极地研究的东西，我们的 ODM 合作伙伴对此保持一致。到明年这个时候，我将有一份关于它的进展报告！
今年的 OIP 论坛主题为“以领导力生态系统扩展 AI”，展示了台积电及其合作伙伴如何加速 AI 芯片设计。了解更多
台积电
By
Aveek Sarkar, Director, Ecosystem and Alliance Management Division, TSMC
09.24.2026
0
TSMC is introducing AI Design Kit to enable the future of AI-driven workflows
In this conversation, Aveek Sarkar, director of the ecosystem and alliance management at TSMC, shares updates on the foundry’s Open Innovation Platform (OIP) Ecosystem, including TSMC’s vision for enabling AI-driven agentic workflows using the new TSMC AI Design Kit (ADK).
What sparked TSMC’s decision to create the Open Innovation Platform (OIP) Ecosystem, and how has it evolved into the “Leadership Ecosystem” today that is essential to driving the AI expansion?
As TSMC built out the pure-play foundry model, the OIP ecosystem has democratized the silicon innovation side.
Our goals are very simple – how do you streamline the customer design process, how do you accelerate their schedule, and how do you de-risk everything they do to get to a successful tape-out and get to revenue? This is a mission on which we, across our 90+ members in our six alliances, are in complete alignment.
By Aveek Sarkar, Director, Ecosystem and Alliance Management Division, TSMC 09.24.2026
By Skyeast International Group Limited 09.24.2026
By Global Unichip Corp. (GUC) 09.22.2026
When you look at our 100,000+ IPs and our reference flows, the description of it as a leadership ecosystem is pretty apt. But leadership is not just about doing things today. It’s about looking around the corner and thinking about what we need to do to pre-empt our customers’ needs.
This is why we’re supporting our customers with emerging design solutions that we are sharing at our OIP event. We have six startups working on AI-based EDA or enabling AI through their IP to join us. We are expanding our support to enable the entire agentic AI infrastructure to evolve quickly.
We also have a new system-level focus that looks beyond the chip and advanced packaging to focus at the rack level, to help ODMs who may not strictly be within our OIP ecosystem, but they are within our customers’ ecosystems. We want to help them and bring our ecosystem to support them.
This is how we’ve evolved. But none of this is possible without commitment from our OIP partners, and we are immensely grateful for everything they do for us and our customers.
Milestones in the evolution of TSMC’s Open Innovation Platform® (OIP) (Source: TSMC)
Energy efficiency is arguably the biggest challenge facing AI expansion today. How is TSMC working with OIP partners to leverage TSMC’s advanced processes, packaging, and COUPE technologies to meet the massive performance and power demands of AI infrastructure?
I think that’s one thing we can all be in full agreement on – we all need energy efficiency!
We look at it from three angles: compute, integration (with memory), and connectivity.
For compute, we have DTCO [design technology co-optimization], TSMC’s approach to developing circuit-level IP and process technologies in tandem to deliver the full potential of power, performance, and area (PPA) benefits.
But it isn’t just DTCO. DTCO gets the technology ready, but customers should be able to use it, and this is where our ecosystem steps in. We work with our partners to enable these flows, and then to deploy them effectively to customers and support them through that process. Our design services and value chain alliances enable that.
As well as digital compute, we also focus on analog, especially since I/O circuits are so energy-critical. We work with our partners from the early stages of PDK development so they can give us feedback, so we can optimise analog PPA.
At the system level, we have TSMC-SoIC [system-on-integrated chips, TSMC’s 3D chiplet-stacking technology], but we need to make sure we address all the associated multi-physics effects – thermal, stress. This is where collaboration with the ecosystem is really critical, because we can create the solution, but customers have to design with it.
For connectivity, the TSMC COUPE is a game-changing technologY, but you have to optimise the electrical and optical components simultaneously. Electromagnetic extraction at the highest fidelity is critical, while thermal has a very big effect on performance. We have to model that also. Of course, it isn’t only these three areas. We are starting to think about the system: the chip in a package with its connectivity, but in a rack or in an IoT platform – how do we address the design challenges? We are expanding our focus within the ecosystem to deliver on that.
How is AI adoption progressing within design tools themselves? How does TSMC collaborate with EDA partners to integrate AI into design workflows to improve productivity?
We’re introducing the TSMC AI Design Kit (ADK) to accelerate time-to-market by enabling agentic AI-based design tools and flows built on TSMC technology-specific learning. This initiative boosts digital design productivity by 3x to 5x, and analog/RF design productivity by up to 6x.
Today, although our reference flows enable customers to achieve significant results, they often still need to perform manual tuning and workflow optimization based on their unique requirements. Going forward, we expect an agentic framework to accelerate these circuit- and architecture-specific optimizations. Unlike a reference flow with static conditions, the TSMC ADK provides a technology knowledge layer to the agentic framework, enabling it to tune optimally and meet design-specific targets quickly. While we expect to learn a lot as we engage with customers, having this framework in place will allow us to drive progress very quickly.
We are very excited about agentic frameworks because of the opportunities for self-learning, self-correcting processes. But this AI journey isn’t new for us – we started several years ago with reinforcement learning in circuit optimization and design space exploration. We work with partners to make sure their tools are ready.
For example – for analog, we have a methodology that can help migrate designs between process nodes. Generative AI opened up new possibilities, but with agentic AI, the possibilities are even bigger. We’ll be working with the partners on the TSMC ADK, and we believe this will be the framework that will enable us to support this build-out.
TSMC’s vision for AI-driven design flows (Source: TSMC)
As AI workloads expand from hyperscale data centers to edge computing, how do TSMC’s design solutions address energy efficiency requirements at the edge versus in the cloud?
Any system deployed at scale will have concerns about performance, energy, and cost, but at the edge, it’s centred around energy and cost. What’s becoming clear is that customer trends [for edge chips] are very clearly heading for the FinFET nodes, to take advantage of the energy benefits. Our ultra-low leakage SRAM allows very low standby power scenarios, so you can add a lot more memory, or you can reduce the voltage, which allows significant dynamic power reduction.
FinFET CAGR is growing steadily in edge applications (Source: TSMC)
From the ecosystem perspective, we are working with our partners to make sure customers have access to the IP they need, which is tuned for their application and their power and cost envelopes.
For example, one of our IP Alliance partners collaborated with our customer, Ambiq, to enable custom IP solutions on TSMC’s N12e process. Through this collaboration, they achieved significant leakage power savings, empowering Ambiq’s edge AI applications.
How is this ecosystem collaboration driving tangible, real-world success for customers? Could you share a recent example where OIP collaboration solved a particularly complex performance or energy efficiency challenge?
Our collaboration with OIP ecosystem partners has been at our core since day one. Over the last 18 years since its formal establishment, the OIP ecosystem has become the driving force enabling customer innovation—from industry leaders to emerging startups.
As our customer keynote speaker at this year’s NA OIP Forum, Greg Dix, VP of Engineering for the ASIC Product Division at Broadcom, showcased how they leverage TSMC’s leading-edge technologies—backed by our robust design ecosystem—to build their latest custom XPU platforms at scale. His presentation highlighted their success in advanced node adoption, heterogeneous multi-die integration, and near-memory co-design. Broadcom is one of many pioneers partnering with us on groundbreaking AI silicon, and it is the collective power of our design ecosystem partners that makes these successes possible.
Every day, there is work happening with partners across the board to help customers tackle unprecedented performance and energy-efficiency design challenges, especially amidst the rapid rise of AI. As an example, this year, we collaborated with SK hynix, Samsung Memory, and Micron on the validation of HBM5 CoWoS [Chip-on-Wafer-on-Substrate]. This was a joint project with each partner looking at best practices, aligning DTCO on thermal-mechanical stress challenges.
TSMC’s advanced nodes are enabling workload-specific architectures (Source: TSMC)
We are also working with our partners, notably our EDA partners, to create reference methodologies and best practices, which we will accelerate with the AI Design Kit. That is critical for customers because it reduces the friction they experience and lowers the barrier to the PPA they are looking for. This year we worked with the three major EDA vendors to organize advanced training for the design services community to level up their expertise, which helps our customers de-risk and reach their targets faster. That had a tangible outcome we are already seeing.
Another example is with COUPE, where electrical and optical parts of the system have to be co-optimized within a compact form factor. We also need to pay attention to thermal properties and electromagnetic interference, which have to be modeled carefully. Some partners and customers will present papers on this subject at this year’s OIP Ecosystem Forum Event.
Looking ahead, what’s next for the OIP ecosystem? How will TSMC and its partners continue to collaborate to enable customer design success amidst the accelerated pace of the AI era?
Each technology transition brings new challenges, but also new opportunities.
People are using agentic AI for individual steps (like root cause analysis) and starting to try out orchestrated flows, where multiple agents work with each other and share information during the design cycle. But it’s quickly becoming apparent to our customers that they need quick feedback on the ramifications of their design decisions in terms of timing, parasitics or thermals. Agents work faster, they can work all night, so they can shorten these feedback loops dramatically. This opens up opportunities for innovation around next-generation engines leveraging hardware acceleration to support the rapid turnaround times needed by agentic workflows. There are also opportunities to use customized LLMs to predict design tradeoff choices.
Customers ask us whether we have looked at this and how we’re enabling it. So what we have to do going forward will need to be much broader, especially with AI design enablement, where we’re just starting to scratch the surface.
The second thing is our system-level focus, which is a new muscle we are now building. Obviously, we have deep expertise on the chip and packaging side, but how do we look at it from a data center point of view, a humanoid robot point of view, or an IoT system point of view? The system is something we are looking at very aggressively, and our ODM partners are aligned on that. I’ll have a progress report on it by this time next year!
This year’s OIP forum, themed “Expanding AI with Leadership Ecosystem,” shows how TSMC and its partners accelerate AI chip design. Learn more
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