TSE扩大下一代HBM堆叠DRAM测试业务
TSE正加速供应测试载具，用于下一代高带宽存储器（HBM）中堆叠DRAM的测试。该测试称为已知良好堆叠芯片（KGSD）测试，用于确定堆叠DRAM是否合格。此举与半导体供应链中HBM测试环节相关。
原文深度解读
本文报道了TSE公司加速供应用于下一代高带宽存储器（HBM）中堆叠DRAM测试的载具，重点介绍了KGSD测试的引入及其技术细节。文章提及TSE高管Baek Dae-hyun在2026年AI半导体测试与插座技术会议上的发言，涉及HBM4E及后续产品的测试需求、技术参数（如对准精度、间距、温度范围、寿命）以及TSE的自动化解决方案。该内容与半导体供应链中HBM测试环节紧密相关，反映了测试成本与良率管理的趋势。
- TSE正在加速供应用于堆叠DRAM测试的载具，KGSD测试预计从HBM4E开始引入。
- KGSD测试在HBM4之前未应用于量产，是否引入取决于良率。
- HBM堆叠层数增加使良率管理更关键，KGSD测试在最终封装前验证堆叠DRAM功能。
- 传统HBM测试聚焦于晶圆级或切割后的单个DRAM芯片，堆叠后增加测试会增加时间和成本，但后期发现缺陷的成本更高。
- TSE的KGSD载具支持间距≤110μm、焊盘尺寸≤70μm，对准精度±5μm，工作温度-40°C至200°C，寿命超过22,000次测试循环。
- TSE开发了自动化载具装载机，包括视觉对准和探针尖端自动清洁功能，并内部生产PCB和中介层以快速响应客户需求。
供应链影响
- KGSD测试的引入可能增加HBM生产中的测试环节，从而影响测试设备与载具的供应链需求。
- 随着HBM堆叠层数增加，测试成本可能上升，这可能促使厂商优化测试流程或寻求更高效的测试方案。
- TSE的载具兼容现有处理设备和测试机，可能降低客户更换设备的成本，从而影响测试设备市场的竞争格局。
- TSE内部生产关键材料（如PCB和中介层）可能增强其供应链自主性，但具体影响取决于产能和客户需求。
- 高价值芯片的测试需求可能推动测试服务外包或内部测试能力建设，具体取决于各厂商的良率与成本策略。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
TSE扩大堆叠DRAM测试载具供应，用于下一代HBM
TSE执行副总裁白大贤于8月26日在AI半导体测试与插座技术会议上发言。（照片：THE ELEC）
TSE正加速供应用于下一代高带宽存储器（HBM）中堆叠DRAM测试的载具。已知良好堆叠芯片（KGSD）测试用于确定堆叠DRAM芯片在组装后是否功能正常，预计将从HBM4E开始引入。
TSE执行副总裁白大贤于8月26日在水原会议中心举行的AI半导体测试与插座技术会议上表示，KGSD测试尚未应用于HBM4之前的量产，但预计将在后续世代中根据良率引入。他说：“我们正在准备覆盖从晶圆级到KGSD整个过程的测试解决方案。”
随着HBM堆叠层数增加，良率管理变得更加关键，对KGSD测试的需求也在增加。KGSD在最终封装前验证堆叠DRAM芯片是否功能正常。HBM通过垂直堆叠多个DRAM芯片制成。即使芯片在晶圆级通过检查，堆叠过程中也可能出现缺陷。
传统HBM测试侧重于晶圆级或晶圆切割后的单个DRAM芯片。堆叠后增加测试会增加测试时间和成本。然而，近来更高的HBM堆叠层数和产品价格上涨增加了在生产后期发现缺陷的成本。
“每个单独芯片的价值飙升，”白大贤说。“随着封装组装后失败成本的上升，确保每个已知良好芯片（KGD）变得越来越重要。”他补充说，客户现在愿意承担大量成本以实现哪怕是微小的良率提升。
TSE已将先前用于单个HBM芯片测试的载具应用扩展到KGSD。载具固定芯片并将其电气连接到测试设备。该公司设计该产品以兼容客户现有的处理设备和测试机。
KGSD载具预计将用于测试HBM4E及后续产品。随着下一代HBM接触间距缩小，堆叠DRAM与探针之间的精确对准变得越来越重要。TSE已实现芯片到探针的对准精度为±5微米（μm）。该载具支持间距≤110μm、焊盘尺寸≤70μm。它可在-40°C至200°C的温度范围内工作，寿命超过22,000次测试循环。
TSE还开发了载具装载机以实现KGSD测试自动化。该系统自动将待测芯片装入载具，并使用视觉系统将其与探针对准。测试后，芯片从载具中取出并卸载。还包含自动探针尖端清洁功能以保持接触性能。
“半导体测试正朝着覆盖整个流程的方向发展，以确保不遗漏任何缺陷，”白大贤说。“TSE通过内部生产关键材料（包括印刷电路板（PCB）和中介层），能够快速响应客户需求。”
Baek Dae-hyun, executive vice president at TSE, speaks at the AI Semiconductor Test & Socket Tech Conference 2026 on Aug. 26. (Photo: THE ELEC)
TSE is accelerating efforts to supply die carriers for testing stacked DRAM in next-generation high-bandwidth memory (HBM). Known Good Stacked Die (KGSD) testing, which determines whether stacked DRAM dies are functional after assembly, is expected to be introduced starting with HBM4E.
Baek Dae-hyun, an executive vice president at TSE, said at the AI Semiconductor Test & Socket Tech Conference 2026, held at Suwon Convention Center on Aug. 26, that KGSD testing has not been applied to mass production through HBM4 but is expected to be introduced in subsequent generations depending on yields. "We are preparing test solutions that can cover the entire process from the wafer level through KGSD," he said.
The need for KGSD testing is increasing as higher HBM stack counts make yield management more critical. KGSD verifies whether stacked DRAM dies are functional before final packaging. HBM is made by vertically stacking multiple DRAM dies. Even when dies pass inspection at the wafer level, defects can occur during stacking.
Conventional HBM testing has focused on individual DRAM dies either at the wafer level or after wafer dicing. Adding another test after stacking increases testing time and costs. More recently, however, higher HBM stack counts and rising product prices have increased the cost of discovering defects at later stages of production.
"The value of each individual chip has surged," Baek said. "As the cost of failure after package assembly rises, securing each Known Good Die (KGD) has become increasingly important." He added that customers are now willing to incur significant costs to achieve even incremental yield improvements.
TSE has expanded the application of die carriers previously supplied for individual HBM die testing to KGSD. A die carrier holds a die in place and electrically connects it to test equipment. The company designed the product to be compatible with customers' existing handlers and testers.
The KGSD die carrier is expected to be used for testing HBM4E and later products. As contact pitches shrink in next-generation HBM, precise alignment between stacked DRAM and probes becomes increasingly important. TSE has achieved die-to-probe alignment accuracy of ±5 micrometers (μm). The carrier supports pitches of 110 μm or less and pad sizes of 70 μm or less. It can operate from minus 40 degrees Celsius to 200 degrees Celsius and has a lifespan of more than 22,000 test cycles.
TSE has also developed a die-carrier loader to automate KGSD testing. The system automatically loads the die under test into the carrier and uses a vision system to align it with the probes. After testing, the die is removed from the carrier and unloaded. An automatic probe-tip cleaning function is also included to maintain contact performance.
"Semiconductor testing is moving toward covering the entire process to ensure that not a single defect is missed," Baek said. "TSE can respond quickly to customer requirements by producing key materials, including printed circuit boards (PCBs) and interposers, in-house."