台积电在A16背面供电技术上取得突破
台积电在埃米级半导体制造中取得领先，其A16制程（低于2纳米）在背面供电技术上获得优势。该技术突破标志着先进节点竞争的新进展，对芯片供应链中依赖先进制程的厂商具有潜在影响。
原文深度解读
本文报道台积电在埃米级半导体制造中取得领先，其A16制程（低于2纳米）集成了背面供电技术（SPR），计划于今年第四季度量产。文章涉及台积电、英特尔、三星等主体，关键数字包括A16相比N2P速度提升8%-10%、功耗降低15%-20%、密度提升8%-10%。该技术对依赖先进制程的AI和高性能计算芯片供应链具有潜在影响。
- 台积电已成功开发并验证A16，这是业界首个采用SPR背面供电架构的埃米级CMOS平台。
- A16保留了N2P工艺的栅极密度和NanoFlex设计灵活性，N2P是N2节点的增强版。
- 传统芯片中电源和信号互连均位于芯片正面，随着节点缩小，布线拥塞和IR压降问题加剧。
- 台积电将供电网络完全移至芯片背面，使用垂直背面接触（VB）直接连接晶体管源漏极，同时最小化对正面栅极结构、单元尺寸和布局的改动。
- 与N2P相比，A16在相同功耗下速度提升8%-10%，在相同速度下功耗降低15%-20%，芯片密度提升8%-10%。
- A16制程计划于今年第四季度开始量产，特别适合AI和高性能计算芯片。
供应链影响
- 台积电A16的量产可能增强其在先进制程代工市场的竞争力，影响依赖先进制程的芯片设计公司（如AI加速器厂商）的供应链选择。
- 背面供电技术的采用可能改变芯片设计流程和EDA工具需求，设计生态系统的竞争可能加剧。
- 英特尔和三星的类似技术进展可能影响代工市场的竞争格局，客户可能根据技术成熟度和量产时间调整订单分配。
- A16的量产时间（今年第四季度）可能影响下游AI和高性能计算芯片的上市节奏，取决于台积电的良率和产能爬坡情况。
- 背面供电技术的普及可能对设备、材料供应商（如光刻、沉积、蚀刻设备）产生新的需求，具体影响取决于技术采用率。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
台积电超级电源轨（SPR）背面供电架构的概念图。图片来源：台积电。
台积电在埃米级半导体制造中取得早期领先，其A16制程（低于2纳米的先进节点）在背面供电技术上获得优势。该技术旨在解决传统芯片正面电源和信号布线争夺同一空间所造成的瓶颈。
据业界消息人士18日透露，台积电已成功开发并验证A16，这是业界首个采用其超级电源轨（SPR）背面供电架构的埃米级CMOS平台。关键成就在于A16保留了N2P工艺（台积电N2节点的增强版）的栅极密度和NanoFlex设计灵活性。
在传统半导体芯片中，电源互连和信号互连均位于芯片正面。随着工艺节点缩小，两者日益争夺有限的布线空间，导致布线拥塞加剧，以及电阻相关的电压降（通常称为IR压降）问题。
实施背面供电通常需要对晶体管布局和标准单元结构进行大幅改动。在更先进的节点，通过芯片背面供电往往意味着牺牲部分现有单元库和设计方法。
台积电将供电网络完全分离到芯片背面，并使用专用的垂直背面接触（VB）将电源直接连接到每个晶体管的源极和漏极区域。该公司在实现这一目标的同时，对正面栅极结构、单元尺寸和布局占用进行了最小改动，从而保持了与现有芯片设计的兼容性。
性能提升也相当可观。与N2P相比，A16在相同功耗下速度可提升8%至10%，或在相同速度下功耗降低15%至20%。芯片密度也可提升8%至10%。
该工艺被认为特别适合AI和高性能计算芯片，这些芯片需要复杂的信号布线和密集的电源网络。A16制程计划于今年第四季度开始量产。
英特尔较早通过其PowerVia技术实现了背面供电商业化，但在测试期间不得不修改其现有单元架构，包括调整引脚数量和放宽金属间距。据报道，三星电子也正在为其SF2工艺追求背面供电，可能采用与英特尔类似的方法。
“这一成就可以在提高效率的同时，减轻AI加速器等产品的设计负担，这些产品必须兼顾电源效率和性能，”一位行业消息人士表示。“在埃米时代，竞争不仅在工艺技术领域加剧，还延伸至设计生态系统。”
Concept image of TSMC's Super Power Rail (SPR) backside power-delivery architecture. Image=TSMC.
TSMC has taken an early lead in angstrom-class semiconductor manufacturing by securing an advantage in backside power delivery for its A16 process, an advanced node below 2 nanometers. The technology is designed to address bottlenecks caused by power and signal routing competing for the same space on the front side of conventional chips.
According to industry sources on the 18th, TSMC has successfully developed and validated A16, the industry's first angstrom-class CMOS platform to incorporate its Super Power Rail (SPR) backside power-delivery architecture. The key achievement is that A16 preserves the gate density and NanoFlex design flexibility of the N2P process, an enhanced version of TSMC's N2 node.
In conventional semiconductor chips, both power interconnects and signal interconnects are placed on the front side of the die. As process nodes shrink, the two increasingly compete for limited routing space, leading to more severe wiring congestion and higher resistance-related voltage drops, commonly known as IR drop.
Implementing backside power delivery has typically required substantial changes to transistor placement and standard-cell structures. At more advanced nodes, supplying power through the back of the chip often means sacrificing portions of existing cell libraries and design methodologies.
TSMC separates the power-delivery network entirely onto the backside of the die and uses dedicated vertical back-side contacts, or VBs, to connect power directly to the source and drain regions of each transistor. The company achieved this while making minimal changes to the front-side gate structure, cell dimensions and layout footprint, preserving compatibility with established chip designs.
The performance gains are also substantial. Compared with N2P, A16 can deliver 8% to 10% higher speed at the same power level, or reduce power consumption by 15% to 20% at the same speed. Chip density can also improve by 8% to 10%.
The process is considered particularly well suited for AI and high-performance computing chips, which require complex signal routing and dense power networks. Mass production of the A16 process is scheduled to begin in the fourth quarter of this year.
Intel, which commercialized backside power delivery earlier with its PowerVia technology, had to modify its existing cell architecture during testing, including adjustments to pin counts and relaxed metal pitches. Samsung Electronics is also reported to be pursuing backside power delivery for its SF2 process, likely through an approach similar to Intel's.
“This achievement can improve efficiency while reducing design burden for products such as AI accelerators, which must secure both power efficiency and performance,” an industry source said. “In the angstrom era, competition is intensifying not only in process technology but also across the design ecosystem.”