三星采用台积电验证的光子学测试平台
三星电子已为其硅光子学开发项目选定与台积电相同的测试设备供应商。硅光子学技术利用光来减少半导体瓶颈和发热。此举表明三星在先进封装领域追赶台积电，相关测试设备需求或增加。
原文深度解读
本文报道三星电子为其硅光子学开发项目选定了与台积电相同的测试设备供应商（美国FormFactor和台湾MPI），计划年底前完成PIC晶圆内部测试。文章涉及三星、台积电、imec、博通等主体，时间点为2026年9月7日及未来规划（2027年推出代工服务）。关键数字包括年底完成测试、2027年推出服务。这与电子元器件供应链相关，因为测试设备需求可能增加，且三星追赶台积电在先进封装领域的布局。
- 三星电子已选定美国FormFactor和台湾MPI作为其硅光子学PIC晶圆测试的探针台供应商，这两家公司也是台积电COUPE平台验证所用供应商。
- 三星计划在年底前完成PIC晶圆内部测试，此前自去年起将验证外包给imec等机构。
- 测试设备用于测量波长域和频域特性，验证光器件的光传输和电光转换。
- 三星在第一季度财报中宣布已获得一家主要光通信模块公司的项目，并计划下半年量产。
- 三星计划2027年推出硅光子学代工服务，提供光器件工艺技术、器件库和PDK。
- 三星最终目标是将光引擎与逻辑芯片和HBM封装在一起，并已展示逻辑芯片和光引擎在硅中介层上的结构。
供应链影响
- 三星采用与台积电相同的测试设备供应商，可能增加对FormFactor和MPI探针台的需求，具体取决于三星量产规模。
- 三星建立内部测试环境可能减少对外部验证机构（如imec）的依赖，影响相关服务需求。
- 三星硅光子学代工服务的推出可能加剧与台积电在先进封装领域的竞争，影响客户选择。
- 若三星CPO应用扩展到GPU和CPU，可能带动相关测试设备需求增长，但取决于技术成熟度。
- 三星获得光通信模块公司项目并计划量产，可能影响光模块供应链，但具体影响取决于订单量。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
三星电子在2026年8月ASPS上展示的共封装光学（CPO）模型。（照片：THE ELEC）
三星电子已为其硅光子学开发项目选定了与台湾台积电相同的测试设备供应商。硅光子学是一种利用光来减少半导体瓶颈、发热和功耗的技术。三星计划在今年年底前完成硅光子学光子集成电路（PIC）晶圆的内部测试。
据业内人士9月7日透露，三星正在使用美国FormFactor和台湾MPI的探针台测试硅光子学PIC晶圆。探针台连接到光学和电学测量设备，以测量波长域和频域的特性。关键在于验证晶圆上制造的光器件是否按设计传输光，并正确实现电信号和光信号之间的转换。
探针台用于测量半导体器件的特性。它们固定晶圆或单个芯片，并将携带电信号的探针连接到电极，从而将器件与外部测量设备连接。硅光子学探针台增加了将光纤与PIC的光输入输出端口精确对准的能力。测量设备发送光信号和电信号并测量输出，而探针台移动晶圆以重复测试每个芯片。
“三星电子正在进行自己的PIC晶圆评估，目标是在年底前完成，”一位行业官员表示。“它使用的是两家供应商的探针台，这两家供应商已通过台积电对CPO和硅光子学测试的设备认证。”
台积电使用FormFactor和MPI的探针台来开发和验证其基于硅光子学的共封装光学（CPO）平台COUPE。到目前为止，这两家公司是唯一通过台积电CPO相关测试设备认证流程的探针台供应商。
自去年以来，三星一直将PIC晶圆验证外包给包括比利时半导体研究机构imec在内的外部组织。现在它已经建立了自己的测试环境，并正在进行重复评估。该公司正处于优化阶段，根据其初始设计评估PIC晶圆的性能，并将测量结果反馈到设计过程中。
三星还在为客户评估做准备。包括博通在内的全球网络和通信半导体公司被认为是潜在客户。三星在第一季度财报中表示，它已获得一家主要光通信模块公司的项目，为其硅光子学业务奠定了基础。它表示该项目的量产将在下半年开始。
PIC集成了光器件，包括传输光的波导、将电信号转换为光信号的调制器，以及将光信号转换为电信号的光电探测器。三星测量波长域和频域的特性，以优化光损耗、波长响应和带宽。
在PIC测试之后，三星计划将测试扩展到将电子集成电路（EIC）与PIC结合的光引擎。EIC处理和放大电信号以驱动PIC的光器件。光引擎通过堆叠EIC和PIC并集成将它们连接到外部光纤的光路而形成。在光引擎测试期间，预计将增加时域测量，以验证实际的高速数据传输性能。
三星计划于2027年推出硅光子学代工服务。它将提供光器件工艺技术、光器件库和工艺设计套件（PDK）。客户将使用这些技术设计PIC，然后由三星代工厂以晶圆形式制造。三星今年开始开发结合EIC和PIC的光引擎，并计划明年开始测试。
最终目标是将光引擎与逻辑芯片和高带宽存储器（HBM）封装在一起。在最近展示的模型中，三星展示了一种结构，其中逻辑芯片和光引擎一起放置在硅中介层上。光引擎内部的PIC和EIC使用混合键合等技术垂直堆叠，以缩短连接距离。三星计划最终将CPO应用从网络交换机扩展到GPU和CPU。
“我们目前正在自行开发包括PIC在内的光器件，”三星电子半导体研发中心先进封装实验室副总裁Choi Won-kyung在7月的Nano Korea上表示。“我们计划进入硅光子学市场，重点是开发集成EIC、PIC和光连接的光引擎，然后将其应用扩展到交换机、GPU和CPU。”
A co-packaged optics (CPO) mockup unveiled by Samsung Electronics at ASPS 2026 in August. (Photo: THE ELEC)
Samsung Electronics has selected the same test equipment suppliers used by Taiwan's TSMC for its silicon photonics development, a technology that uses light to reduce semiconductor bottlenecks, heat generation and power consumption. Samsung plans to complete in-house testing of photonic integrated circuit (PIC) wafers for silicon photonics by the end of this year.
According to industry sources on Sept. 7, Samsung is testing silicon photonics PIC wafers using probe stations from US-based FormFactor and Taiwan-based MPI. The probe stations are connected to optical and electrical measurement equipment to measure characteristics in the wavelength domain and frequency domain. The key is to verify whether optical devices fabricated on the wafer transmit light as designed and properly convert between electrical and optical signals.
Probe stations are used to measure the characteristics of semiconductor devices. They hold a wafer or individual die in place and connect probes carrying electrical signals to electrodes, linking the device to external measurement equipment. Silicon photonics probe stations add the ability to precisely align optical fibers with the optical input and output ports of a PIC. Measurement equipment sends optical and electrical signals and measures the outputs, while the probe station moves the wafer to repeatedly test each die.
"Samsung Electronics is conducting its own evaluation of PIC wafers with the goal of completing it by year-end," an industry official said. "It is using probe stations from the two suppliers that have passed TSMC's equipment qualification for CPO and silicon photonics testing."
TSMC uses probe stations from FormFactor and MPI to develop and validate COUPE (Co-Packaged Optical Engine), its silicon photonics-based co-packaged optics (CPO) platform. So far, the two companies are the only probe station suppliers to have passed TSMC's qualification process for CPO-related test equipment.
Samsung had outsourced PIC wafer validation to external organizations including Belgium-based semiconductor research institute imec since last year. It has now established its own testing environment and is conducting repeated evaluations. The company is at the optimization stage, evaluating the performance of PIC wafers based on its initial designs and feeding measurement results back into the design process.
Samsung is also preparing for customer evaluations. Global networking and communications semiconductor companies including Broadcom have been cited as potential customers. Samsung said during its first-quarter earnings announcement that it had secured a project from a major optical communications module company, establishing a foundation for its silicon photonics business. It said mass production for the project would begin in the second half.
A PIC integrates optical devices including waveguides that carry light, modulators that convert electrical signals into optical signals, and photodetectors that convert optical signals into electrical signals. Samsung measures characteristics in the wavelength and frequency domains to optimize optical loss, wavelength response and bandwidth.
After PIC testing, Samsung plans to expand testing to optical engines that combine an electronic integrated circuit (EIC) with a PIC. The EIC processes and amplifies electrical signals to drive the PIC's optical devices. An optical engine is formed by stacking the EIC and PIC and integrating optical paths that connect them to external optical fibers. Time-domain measurements are expected to be added during optical engine testing to verify actual high-speed data transmission performance.
Samsung plans to launch silicon photonics foundry services in 2027. It will provide optical device process technologies, optical device libraries and process design kits (PDKs). Customers will use these technologies to design PICs, which Samsung Foundry will manufacture in wafer form. Samsung began developing optical engines combining EICs and PICs this year and plans to begin testing them next year.
The ultimate goal is to package the optical engine together with logic chips and high-bandwidth memory (HBM). In a recently unveiled mockup, Samsung showed a structure in which a logic chip and optical engine are placed together on a silicon interposer. The PIC and EIC inside the optical engine are vertically stacked using technologies including hybrid bonding to shorten connection distances. Samsung plans to eventually expand CPO applications from network switches to GPUs and CPUs.
"We are currently developing optical devices including PICs ourselves," Choi Won-kyung, vice president of Samsung Electronics' Semiconductor R&D Center Advanced Package Lab, said at Nano Korea in July. "We plan to enter the silicon photonics market by focusing on developing an optical engine that integrates EICs, PICs and optical connections, and then expand its application to switches, GPUs and CPUs."