Marvell瞄准AI瓶颈,推出内存解聚产品组合
Marvell推出内存解聚产品组合,包括SSD、CXL和光子结构,旨在将数据更靠近计算,以解决AI内存瓶颈问题。该产品组合涉及Marvell公司,具体型号未提及。
原文深度解读
本文介绍了Marvell Technology推出的内存解聚产品组合,旨在解决AI工作负载中的内存瓶颈问题。产品包括Bravera SC6 PCIe 6.0 SSD控制器、Structera CXL系列(用于内存扩展和池化)以及光子结构(Photonic Fabric)组件。文章涉及Marvell公司、其产品经理Khurram Malik、以及Meta等客户。关键数字包括Structera X压缩能力可提供约2至2.5倍的有效内存容量,光子结构支持50米距离和32 TB的KV缓存卸载,并声称可提升2至3倍的令牌吞吐量。这些产品与电子元器件供应链相关,因为它们涉及SSD控制器、CXL交换机和光学组件,影响数据中心基础设施的采购和部署。
- Marvell推出内存解聚产品组合,包括Bravera SC6 PCIe 6.0 SSD控制器、Structera CXL系列和光子结构组件,旨在将内存更靠近计算点,减少数据瓶颈。
- Bravera SC6控制器支持跨NAND供应商,提供灵活性,并采用主机管理的闪存转换层,允许客户控制写放大、垃圾回收和磨损均衡。
- Structera X支持DDR4/DDR5内存复用,压缩能力可提供约2至2.5倍的有效内存容量;Meta正在数百万台服务器上使用CXL内存扩展,复用退役机器的DDR4模块。
- Structera A是近内存计算加速器,用于推荐引擎、向量搜索、数据库和HPC;Structera S4是CXL 3.1交换机,支持协议转换。
- 光子结构通过光链路支持跨机架共享内存,距离可达50米,支持32 TB的KV缓存卸载,并声称可提升2至3倍的令牌吞吐量,但实际收益取决于工作负载和系统实现。
- Marvell认为AI性能的下一个提升不仅来自更快的处理器,还来自更好的内存存储、池化和移动方式,并与超大规模客户合作实现解聚。
供应链影响
- Marvell的新产品可能影响数据中心内存和存储的采购决策,因为客户可能更倾向于采用支持内存解聚的控制器和CXL设备,从而改变对传统内存模块和SSD的需求。
- Bravera SC6控制器对NAND供应商的广泛支持可能使超大规模客户在供应受限时拥有更多选择,这可能影响NAND闪存供应商的市场份额和定价策略。
- Structera X对DDR4/DDR5的复用可能延长旧内存模块的生命周期,减少对新内存的需求,这可能影响内存制造商的生产计划。
- 光子结构的部署可能增加对光学组件和互连设备的需求,这可能影响光模块和光纤供应链。
- 这些产品的采用取决于数据中心架构的升级和客户的工作负载特性,可能影响相关电子元器件的库存和交付周期。
系统解读,仅作为判断线索,不构成备货、出货、涨价或投资建议。
Marvell Technology最新的内存基础设施产品旨在帮助超大规模和云客户将内存移动到更靠近计算点的位置,减少数据瓶颈,并提高推理工作负载的令牌效率。
在与EE Times的简报中,产品营销副总裁Khurram Malik表示,此次发布涵盖三个“泳道”,它们都属于同一内存解聚策略的一部分。该产品组合包括Marvell的Bravera SC6 PCIe 6.0 SSD控制器、用于内存扩展和池化的Structera CXL系列,以及用于光学共享内存架构的光子结构组件。
Malik表示,目标是让云提供商在日益严苛的AI工作负载中,在如何获取、扩展和分配内存方面拥有更大的灵活性。他说,这些产品共同解决了AI基础设施堆栈的三个层面:服务器附加存储、机架级内存扩展和池化,以及跨多个机架分布的共享内存。
实现更好的NAND控制
Bravera SC6旨在支持服务器级AI存储用例,包括键值缓存,在SSD上保留更多数据可以提高基础设施效率,Malik表示客户已经在采用这一趋势。
作者:Raphi Zadicario,Lumissil Microsystems产品经理兼首席架构师,2026年8月17日
作者:Krizelle Paulene Apostol,软件系统工程师;Jamila Macagba,高级软件系统工程师;Maggie Maralit,软件系统设计工程经理,2026年8月13日
作者:Isaac Lopez,OmniScale Media总裁;Charity Plata,SC26通信主席,2026年8月13日
他说,Bravera SC6控制器对超大规模客户的吸引力在于它对NAND供应商的广泛支持,在供应限制影响采购决策时为客户提供灵活性。
Malik表示,Bravera SC6控制器也反映了超大规模客户越来越希望根据工作负载需求调整存储行为。它围绕主机管理的闪存转换层构建,允许客户更好地控制写放大、垃圾回收和磨损均衡。
“最终客户了解他们的工作负载,”他说。“他们根据工作负载在NAND上写入,并管理写放大,这转化为SSD的耐久性。”
Marvell的Bravera SC6 PCIe 6.0 SSD控制器旨在支持服务器级AI存储用例,包括键值缓存,在SSD上保留更多数据可以提高基础设施效率。(来源:Marvell Technology)
为AI工作负载池化内存
Compute Express Link(CXL)协议的出现早于最近的AI热潮,但它正迅速成为AI基础设施的关键推动力。
Malik表示,用于内存扩展和池化的Structera CXL系列反映了Marvell如何将自己视为新兴CXL市场中的广泛产品组合参与者。
他说,公司的Structera X内存扩展能力允许复用现有的DDR4或DDR5容量,这可能是超大规模客户在数据中心寻求快速部署路径时的第一个采用点。“CXL中最重要的用例是DDR4的回收利用。”
一个高知名度的例子是Facebook母公司Meta,它正在数百万台服务器上使用基于CXL的内存扩展,复用从退役机器中取出的DDR4模块,而不是淘汰它们。
Malik表示,Structera X的压缩能力可以提供约2至2.5倍于标准方法的有效内存容量。
与此同时,Structera A是一种近内存计算加速器,旨在卸载CPU和GPU的工作,Malik表示它专为推荐引擎、向量搜索、数据库和HPC等工作负载而设计。
在机架层面,Structera S4是一款CXL 3.1交换机,可以支持分解内存架构,即使在不存在原生通道的情况下,也能将CPU和GPU连接到CXL资源。“我们在交换机中有一个协议转换层,将PCIe转换为CXL原生协议,”Malik说。
将AI内存扩展到机架之外
Marvell的光子结构产品通过光链路将内存解聚概念扩展到多个机架。它旨在提高具有大内存占用和长上下文窗口的模型的吞吐量。
Malik表示,它可以创建距离最远50米的共享内存层,并支持高达32 TB的温KV缓存卸载。该公司还声称,光子结构可以在现有数据中心占地面积和功率范围内提供2至3倍的令牌吞吐量,但实际收益将取决于工作负载特性和系统实现。
Malik表示,这些产品的共同发布解决了将内存视为固定、服务器本地资源的转变。通过将内存与计算分离,并在不同规模上连接存储、CXL设备和光结构,云运营商可以更动态地分配容量,同时减少孤立资源。
Malik表示,Marvell相信AI性能的下一个提升不仅来自更快的处理器,还来自更好的内存存储、池化和移动方式。“我们正通过与超大规模客户合作,基于他们的架构,站在实现这种解聚的前沿。”
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Marvell Technology’s latest memory infrastructure products aim to help hyperscale and cloud customers move memory closer to the point of computation, reduce data bottlenecks, and improve token efficiency for inference workloads.
In a briefing with EE Times, Khurram Malik, associate VP product marketing, said the rollout spans three “swim lanes,” all of which are part of the same memory-disaggregation strategy. The portfolio includes Marvell’s Bravera SC6 PCIe 6.0 SSD controller, the Structera CXL family for memory expansion and pooling, and the company’s Photonic Fabric components for optical shared-memory architectures.
Malik said the goal is to give cloud providers more flexibility in how they source, scale, and allocate memory across increasingly demanding AI workloads. Together, these products address three levels of the AI infrastructure stack: server-attached storage, rack-scale memory expansion and pooling, and shared memory distributed across multiple racks, he said.
Enabling better NAND control
Bravera SC6 is intended to support server-level AI storage use cases, including key-value cache, where keeping more data on SSD can improve infrastructure efficiency, a trend Malik said customers are already adopting.
By Raphi Zadicario, Product Manager and Chief Architect, Lumissil Microsystems 08.17.2026
By Krizelle Paulene Apostol , Software Systems Engineer, Jamila Macagba , Senior Software Systems Engineer, and Maggie Maralit , Software Systems Design Engineering Manager 08.13.2026
By Isaac Lopez, President, OmniScale Media & Charity Plata, Communications Chair, SC26 08.13.2026
He said the Bravera SC6 controller’s appeal to hyperscalers is its support across NAND suppliers, giving customers flexibility at a time when supply constraints influence purchasing decisions.
The Bravera SC6 controller also reflects the way hyperscalers increasingly want to tune storage behavior to workload needs, Malik said. It is built around a host-managed flash translation layer, allowing customers to better control write amplification, garbage collection, and wear leveling.
“End customers know their workloads,” he said. “They write on the NAND based off of their workload and they manage the write amplification, which turns into the endurance of the SSDs.”
Marvell’s Bravera SC6 PCIe 6.0 SSD controller is intended to support server-level AI storage use cases, including key-value cache, where keeping more data on SSD can improve infrastructure efficiency. (Source: Marvell Technology)
Pooling memory for AI workloads
The advent of the Compute Express Link (CXL) protocol predates the recent AI boom, but it is quickly becoming a key enabler of AI infrastructure.
Malik said the Structera CXL family for memory expansion and pooling reflects how Marvell sees itself as a broad portfolio player in the emerging CXL market.
He said the company’s Structera X memory expansion capabilities allow for the reuse of existing DDR4 or DDR5 capacity, making it a likely first adoption point for hyperscalers looking for quick deployment paths in data centers. “The first and foremost important use case within CXL is the recycling of DDR4.”
A high-profile example is Facebook parent company Meta, which is using CXL-based memory expansion across millions of servers, reusing DDR4 modules pulled from decommissioned machines rather than retiring them.
Malik said Structera X’s compression capabilities can deliver roughly 2 to 2.5× the effective memory capacity compared with standard approaches.
Structera A, meanwhile, is a near-memory compute accelerator built to offload work from CPUs and GPUs, which Malik said is designed for workloads such as recommendation engines, vector search, databases, and HPC.
At the rack level, Structera S4 is a CXL 3.1 switch that can support disaggregated memory architectures designed to connect CPUs and GPUs to CXL resources even when native lanes are not present. “We have a protocol conversion layer which converts PCIe over CXL native in the switch,” Malik said.
Pushing AI memory beyond the rack
Marvell’s Photonic Fabric offering extends the memory-disaggregation idea across multiple racks using optical links. It is designed to improve throughput for models with large memory footprints and long context windows.
Malik said it can create a shared-memory tier up to 50 meters away and support up to 32 TB of warm KV cache offload. The company also claims that the Photonic Fabric can deliver two to three times the token throughput within existing data center footprints and power envelopes, although actual gains will depend on workload characteristics and system implementation.
The rollout of these products together addresses the shift from treating memory as a fixed, server-local resource, Malik said. By separating memory from compute and connecting storage, CXL devices and optical fabrics across different scales, cloud operators can potentially allocate capacity more dynamically while reducing stranded resources.
Malik said Marvell believes the next gains in AI performance will come not only from faster processors, but also from better ways to store, pool, and move memory. “We are in the forefront to enable that disaggregation by working with hyperscalers based on their architecture.”
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Gary Hilson
Gary Hilson is a freelance writer and editor who has written thousands of words for print and pixel publications across North America. His areas of interest include software, enterprise and networking technology, research and education, sustainable transportation, and community news. His articles have been published by Network Computing, InformationWeek, Computing Canada, Computer Dealer News, Toronto Business Times, Strategy Magazine, and the Ottawa Citizen.
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