Articron 凭借下一代存储 IP 挑战 1 万亿韩元估值

Han-ul Jeong, CEO of Articron. (Photo: THE ELEC)

Articron aims to scale its corporate valuation to over 1 trillion KRW by 2030 through next-generation artificial intelligence (AI) memory semiconductor intellectual property (IP).

"Our target is to expand our valuation and achieve an Initial Public Offering (IPO) between 2029 and 2030," said Han-ul Jeong, CEO of Articron.

Articron is a memory IP specialist spun out of Yonsei University, established three and a half years ago. The company currently employs roughly 50 staff members. CEO Jeong, a former SRAM engineer at Samsung Electronics, concurrently serves as a professor in the School of Electrical and Electronic Engineering at Yonsei University.

Recognized for its foundational SRAM technologies, the company was selected for the Ministry of Small and Medium-sized Enterprises (SMEs) and Startups' "Super Gap Startup 1000+" project, receiving funds for commercialization and technology development.

Articron's core business rests on three pillars: standard SRAM IP, automated SRAM design tools, and SRAM Compute-in-Memory (CIM)-based Neural Processing Unit (NPU) IP.

Last year, the company recorded 421 million KRW in revenue with a net loss of 21 million KRW. Standard SRAM IP serves as its primary current revenue source, providing customized SRAM IP integrated into customer chips across major foundry processes, including TSMC and Samsung Electronics, with plans to expand into GlobalFoundries (GF) and UMC processes. SRAM temporarily stores data inside a chip, offering faster processing speeds and lower power consumption than DRAM despite requiring more silicon area.

The company is heavily prioritizing the development of SRAM CIM-based NPU IP due to its high future growth potential. CIM processes computations directly inside memory, minimizing data movement while enhancing computational efficiency. NPUs represent specialized silicon optimized for AI workloads.

Commercial revenue recognition from its NPU IP is expected to require at least two years. The company plans to secure a new funding round in the first half of next year, building on its cumulative funding of approximately 3 billion KRW.

Conventional NPUs fetch data stored in SRAM to execute calculations. In contrast, SRAM CIM-based NPU IP minimizes data transfers, improving both power efficiency and chip area footprint. "Utilizing CIM allows a chip to deliver identical performance while doubling power efficiency," explained CEO Jeong. "Furthermore, the required chip area is halved."

Current development efforts center on IP optimized for Convolutional Neural Networks (CNNs), an AI model family widely used in computer vision for object and human recognition and feature extraction.

Moving forward, Articron plans to release IP targeting Recurrent Neural Networks (RNNs) and on-device Large Language Models (LLMs). RNNs retain historical input data to process sequential speech and text data.

Q&A

Q: You are currently serving as a professor. Did you found the company while in academia?

A: Correct. I was previously in the Department of Electronic Engineering at Kwangwoon University before moving to the School of Electrical and Electronic Engineering at Yonsei University last year. I founded the company about three and a half years ago while serving as a professor at Kwangwoon University.

Q: What is the meaning behind the name "Articron"?

A: As an AI semiconductor company, "Arti" comes from Artificial Intelligence. We combined that with "Creative Association" ("cron") to signify a creative team building proprietary in-house technologies.

Q: Looking at your corporate profile, you initially started with SRAM. Prior to academia, you worked at Samsung Electronics as an SRAM engineer, correct?

A: Yes, I was at Samsung Electronics working on SRAM.

Q: Did you establish the company around SRAM-related business?

A: Rather than traditional SRAM, we focused on next-generation SRAM optimized for AI semiconductors. This structure integrates memory and execution units, known as Compute in Memory (CIM). We founded the company as an SRAM CIM-based AI semiconductor enterprise to commercialize CIM architectures commercially for the first time in Korea.

Q: You also possess SRAM design automation tools. Your model involves selling those tools while providing custom SRAM IP tailored to client chips upon request. Do you intend to expand further into AI silicon?

A: Correct.

Q: SRAM is known for high speed, but it requires substantial silicon area and is expensive. How do you integrate SRAM into AI architectures?

A: Although larger and more costly than DRAM, SRAM remains essential. Memory data throughput is paramount today. AI computations themselves are relatively simple, consisting mostly of basic additions and multiplications. Ultimately, AI workloads require feeding massive amounts of data into these compute units, making memory critical. SRAM is growing increasingly important alongside DRAM. Unlike DRAM, where data travels off-chip, SRAM temporarily stores data on the exact same die as the processing units. If workloads demand high data throughput, retaining large data volumes on-chip becomes necessary, where SRAM plays a crucial role.

Q: Standard DRAM uses a single transistor per cell, whereas SRAM requires more?

A: Conventional SRAM requires a minimum of six transistors to store a single bit of data, though other cell structures exist.

Q: Because each cell requires six transistors, the area footprint is large. Although fast and efficient next to processing units, isn't SRAM at a capacity disadvantage for handling massive data volumes?

A: You've identified the exact challenge. However, even the largest AI models cannot bypass SRAM. SRAM must hold data and feed it to compute units in real time. Fetching data from off-chip DRAM incurs significant latency and energy costs. Therefore, increasing on-chip SRAM capacity dramatically reduces off-chip DRAM access overhead, making SRAM indispensable.

Q: Doesn't incorporating large SRAM capacities increase total chip cost? Is it still cost-effective?

A: It offers distinct economic advantages, though it isn't universally cheaper. Up to an optimal threshold, maximizing SRAM capacity yields far higher operational efficiency.

Q: Meaning that using larger SRAM capacity to eliminate DRAM transfer latency and power consumption yields better net performance for specific workloads, despite higher raw silicon costs?

A: Correct. Beyond silicon costs, post-fabrication power consumption must be evaluated. DRAM requires data to travel off-chip, whereas SRAM transfers data locally on-chip, offering significantly higher power efficiency.

Q: What are your current technical achievements and development status after three and a half years?

A: We possess world-class technical capabilities in SRAM. Regarding commercialization and customization, we have a solid track record of delivering upgraded IP over conventional alternatives. For CIM NPU IP, prospective clients are actively reviewing our designs. By centering AI chip architecture around SRAM, our next-generation architecture executes computations directly where data resides, enabling simultaneous improvements in power efficiency and chip area compared to conventional AI accelerators.

Q: Your core offerings currently comprise SRAM IP, SRAM design automation tools, and SRAM-centric NPU IP?

A: It is clearest to view them as three distinct product families with different target clients and competitive landscapes. While foundries and fabless firms provide or build standard SRAM IP, we balance focus between SRAM IP and SRAM NPU IP, placing heavier emphasis on SRAM NPU IP due to its explosive growth potential.

Q: Few IP providers focus heavily on leveraging SRAM for CIM NPU architectures. Who are your main competitors?

A: Competitors exist globally. No domestic IP providers focus on SRAM CIM-based IP like we do. A few US firms exist, but fully commercialized implementations remain rare industry-wide and are only beginning to emerge.

Q: How is your SRAM-centric compute architecture structured?

A: We develop complete NPUs. Conventional SRAM only handles read and write operations; we integrate arithmetic circuits directly alongside read/write circuitry within the SRAM block, embedding addition and multiplication logic. If a conventional NPU architecture needs to add ten two-digit numbers, it must access SRAM repeatedly ten times. Our architecture converts those ten two-digit numbers into a single three-digit representation, requiring only a single memory access and dramatically improving efficiency.

Q: Does integrating compute functionality require attaching execution logic to every individual memory cell?

A: Not necessarily. While such structures exist, we accommodate dual approaches based on client requirements regarding how many cells share a single compute unit. Sharing one compute unit across multiple cells represents the standard implementation.

Q: Had you been researching this concept even before founding the company?

A: I have worked exclusively on SRAM throughout.

Q: How does Articron differentiate itself from prior academic research and competing implementations?

A: Many theoretical structures evaluated in academia face severe commercialization hurdles due to yield loss or accuracy degradation under real manufacturing conditions. Those structures claiming several-fold, 10x, or 100x gains in papers rarely reach commercialization once real-world yield is considered. We identified optimal structural trade-offs that preserve high yield and accuracy on production silicon. Furthermore, clients require real-time execution across diverse AI models within specific ranges. By providing custom CIM-based AI accelerator IP tailored to their target workload ranges, we deliver superior power and area efficiency compared to legacy architectures.

Q: Have you validated your NPU IP and SRAM CIM IP on actual silicon?

A: Yes, we fabricated test chips to validate functionality on silicon across both academic and corporate projects, and we continue to do so at the company.

Q: Which foundries do you fabricate with?

A: We fabricate at TSMC and Samsung Foundry.

Q: You run these as MPW shuttles, with actual measured results?

A: Yes. Beyond our primary targets of TSMC and Samsung Foundry, we are expanding process support to GF and UMC nodes.

Q: Which process nodes have you taped out on?

A: On TSMC, we have processed down to 28nm and 22nm nodes. On Samsung Foundry, we have tapped advanced nodes, including 14nm, 8nm, and 5nm.

Q: Have you run all of those nodes?

A: On TSMC, we have taped out down to 28nm, and we are currently working on TSMC 22nm as well as Samsung 14nm and 5nm nodes.

Q: Fabrication incurs significant expenses. How do you fund these MPW runs?

A: It is costly. We utilize raised venture capital alongside government-supported R&D projects and national MPW subsidies to execute multi-node tape-outs.

Q: Why fabricate across multiple nodes?

A: As an IP provider rather than a fabless chip maker, we don't target single-node mass production. Because prospective clients utilize diverse foundry nodes, we validate IP across multiple process nodes via MPW runs to ensure broad compatibility.

Q: What do your measured silicon test results indicate?

A: Measured against conventional non-CIM architectures, our silicon results conservatively demonstrate more than a two-fold improvement in power and area efficiency simultaneously. For identical performance levels, power consumption is cut in half; for identical power envelopes, performance doubles—achieving equivalent model accuracy at half the power and footprint.

Q: Is your IP available for general licensing? Who represents your primary target customer base?

A: During our founding, we evaluated market demand for NPU IP. Today, nearly every semiconductor firm seeks to integrate NPUs to accelerate AI workloads within their applications. However, optimizing custom AI accelerators across the full stack—from AI software down to physical IP—is challenging for traditional chip designers. We supply full-stack support, making any fabless or system company seeking low-power AI acceleration a prospective client.

Q: Can CIM IP support on-device Large Language Models (LLMs)?

A: Yes. Supporting LLMs requires pairing CIM with external DRAM, synchronizing execution across memory tiers. We are building platforms tailored to next-generation mobile DRAM and HBM formats, constructing LPDDR PIM-based platforms to optimize on-device LLM execution.

Q: How is that system hierarchy configured?

A: The device employs our NPU with LPDDR PIM as DRAM. The next-generation hierarchy integrates conventional SRAM, our SRAM CIM NPU, and external DDR memory.

Q: What is your current headcount, cumulative funding, and strategic roadmap?

A: We currently employ nearly 50 staff members. Cumulative funding stands at approximately 3 billion KRW. When closing our prior round, we communicated a milestone to investors targeting our next funding round in the first half of 2027. Our goal prior to that round is demonstrating clear customer traction and licensing intent for our NPU IP. Meanwhile, our standard SRAM IP business is actively generating commercial revenue and expanding its client base, progressing smoothly on schedule.

Q: So standard SRAM IP provides stable baseline revenue while CIM NPU IP drives long-term exponential growth?

A: Correct. While initially viewed as a short-term offering, client demand for custom SRAM is substantial due to on-chip standby power and area challenges. Our proprietary internal design automation tools enable us to deliver high-quality custom SRAM IP faster and cheaper than manual layout methods. Thus, SRAM IP represents a long-term core business pillar alongside NPU IP.

Q: You sell the tools and also provide customized SRAM when needed. How much do the tools cost?

A: It varies case by case.

Q: So you sell the tools, provide customized SRAM, and run the NPU IP business as well. Earlier, you set a milestone of "showing visible customers" next year. The phrase "showing" is a bit ambiguous—does it not mean signing contracts?

A: A contract would be ideal, and it could be a contract. In my experience, IP sales are a close-contact business, and it takes a very long time before payment actually comes in. IP involves extensive work tailoring the product to what the customer wants. Some models simply sell a pre-built product, but more often customers try it out in various ways from the start and spend long periods customizing multiple IPs while pre-developing products they will eventually mass-produce. Through that process, there are not only IP license agreements but various other types of contracts between the customer and the IP provider. I'd ask you to understand it in that broader sense.

Q: Is your IP complete?

A: We keep upgrading it. A first version exists, and customers can use it without issue.

Q: In what direction are the upgrades heading?

A: It starts with a CNN focus. We have NPU IP specialized for CNNs, and we continue upgrading structures used for Transformers, RNNs, and on-device LLMs so they become as competitive as the CNN version.

Q: So you have CNN-optimized IP ready, and you are developing RNN and LLM support next?

A: Those are also fairly well developed. Early next year, our CNN IP will go through another MPW run, and in the middle of next year we plan to run the next version via MPW with features that optimally handle on-device LLM and RNN workloads.

Q: Since CNNs are vision-oriented, should we understand your main customers to be companies making vision-related chips?

A: Yes, you can understand it that way.

Q: Should we expect commercial revenue to ramp up around next year or the year after?

A: Chip development takes about two years. Even if we begin discussions with a customer now, it takes time before actual revenue materializes.

Q: There may be early licensing revenue, but volume royalties tied to each product sold will take considerable time?

A: We do not yet have NPU licensing revenue.

Q: Among domestic companies making similar IP, Openedge Technology is listed, with a market capitalization hovering around 200 billion KRW. Articron was valued at 20 billion KRW in its early Pre-Series round. Do you have an internal target for the level of growth at which you should go public?

A: That may be a bit ambiguous to discuss right now. The company you mentioned is also doing well. In the market we are looking at, it will depend on how many customers we secure and how large an impact those customers generate. I expect that company to grow much larger as well. Our internal target is to go public with a valuation of over 1 trillion KRW around 2029 to 2030.

Q: A valuation exceeding 1 trillion KRW is quite high.

A: I don't think it's high.