Kepler 计划于 2027 年推出 HBM 的节能替代方案
Kepler 计划于 2027 年量产 3D 铁电存储器，该产品宣称每瓦带宽比 HBM 高 5 至 10 倍。目前该产品仍处于目标阶段，尚未投产。
原文深度解读
本文介绍成立于2018年的Kepler Computing公司，其计划于2027年量产可替代HBM和SRAM的存储器，宣称每瓦带宽比HBM高5至10倍，容量至少为SRAM的10倍。公司已与GlobalFoundries合作并自建晶圆厂，采用3D单片堆叠和铁电存储技术，声称无需依赖EUV即可实现先进节点，且2027年产能已全部分配。该产品若按计划落地，可能对AI芯片中HBM与SRAM的供应链格局产生影响。
- Kepler成立于2018年，计划在2027年开始生产针对AI芯片中HBM和SRAM“瓶颈”的存储器，并已准备好与产业伙伴合作进入大规模制造；Intel Capital是其投资方。
- Kepler已与GlobalFoundries合作生产，并自建晶圆厂以推进其专有3D和铁电存储技术；公司认为在客户既有晶圆厂旁建设小型Kepler晶圆厂，可用相比新建先进节点十分之一的投资，跨越多个世代进入领先节点。
- Kepler称其存储器每瓦带宽比HBM高5至10倍，容量至少是SRAM的10倍；其中一款可视为HBM替代品，另一款可视为SRAM替代品。
- Kepler实现了芯片内器件的单片堆叠，避免了热问题，因此可避免使用EUV；底层晶体管可用EUV制造，但公司不要求缩小该晶体管，而是通过堆叠新器件来分摊其使用。
- Kepler CTO表示其技术将存储密度提高2至3倍，并与CMOS兼容；Intel Capital董事总经理称SRAM微缩已在约5nm左右结束，而Kepler可利用后段制程获得高于边界节点的密度。
- Kepler拒绝透露铁电存储器的材料细节，理由是担心外国对手知晓材料后可绕过EUV；公司称过去约七年经历了数千次迭代来发现该铁电材料。公司表示2027年全部产能已分配，拒绝透露除GlobalFoundries外的客户和合作伙伴名称，仅称其涉及AI数据中心和制造业，长期还计划开发逻辑芯片。
供应链影响
- 如果Kepler按计划在2027年量产，AI芯片用HBM和SRAM的供应来源可能增加一个替代选项，但实际影响取决于其良率、产能规模和客户导入进度。
- Kepler声称无需依赖EUV即可达到先进节点，这可能降低对EUV设备和先进制程产能的依赖，但底层晶体管仍可能使用EUV，因此对EUV供应链的影响可能是部分的。
- Kepler自建晶圆厂并与GlobalFoundries合作，可能形成新的存储器制造与封装环节，但具体供应链结构取决于其量产地点和合作模式。
- Kepler称2027年产能已全部分配，这可能意味着初期供应量有限，对整体HBM和SRAM市场的替代作用可能较小，具体取决于分配规模和客户类型。
- Kepler对铁电材料保密，可能使该技术的供应链高度集中且不透明，下游客户在材料来源和产能保障方面可能面临不确定性。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
Kepler 计划于 2027 年推出节能型 HBM 替代品
Kepler Computing 成立于 2018 年，公司高管告诉 EE Times，其目标是在明年开始生产可解决 AI 芯片中 HBM 和 SRAM“瓶颈”的存储器。Kepler 的投资方 Intel Capital 表示，该公司已准备好与行业伙伴合作，进入大规模制造。
该公司已与 GlobalFoundries 合作生产，并自建晶圆厂以加速其专有 3D 和铁电存储技术。公司认为，在客户既有晶圆厂旁建设一个小型 Kepler 晶圆厂，可以帮助以相比新建先进节点十分之一的投资，跨越多个世代进入领先节点。
Kepler 表示，其预计与 GlobalFoundries 等伙伴合作制造 AI 芯片，无需依赖 EUV 即可达到先进节点。
“我们看起来就像美光、SK 海力士或三星，”Kepler CEO Debo Olaosebikan 告诉 EE Times。“客户只是从我们这里购买存储模块，然后将其集成到他们的芯片中。”
作者：MRPeasy 2026年10月1日
作者：Francesca Pinto，SPEA Electronic Test Products 文案 2026年10月1日
作者：Dr. Jim Shiely，Siemens EDA 技术与战略顾问 2026年9月30日
AI 模型正在给传统存储架构带来压力。这些压力表现为 DRAM 和 HBM 设计与制造成本上升、能耗和散热增加，以及可扩展性选项减少。AI 数据中心也在给电网带来压力。AI 设施中消耗的大部分能源都花在 GPU 与 HBM 之间的数据读取上。
Kepler 联合创始人 Amrita Sasi Debo Rajeev 和 Ramesh
单片堆叠
Olaosebikan 表示，公司已实现芯片内器件的单片堆叠，从而避免了热问题。
“这就是为什么我们可以避免 EUV，”他说。“我可以采用旧的大晶体管，但只是使用更少的数量，并把东西堆叠在那个晶体管之上。”
底部的晶体管可以用 EUV 制造。
“我们对此没问题，”Olaosebikan 说。“无论基础节点是什么，我们都不强求必须缩小那个晶体管。我们将通过堆叠在其上的新器件来分摊该晶体管的使用。”
“我们将存储密度提高了两到三倍，而且它实际上与 CMOS 兼容，”Kepler CTO Sasi Manipatruni 告诉 EE Times。
Intel Capital 董事总经理 Srini Ananth 告诉 EE Times，公司已达到准备好与行业伙伴合作的阶段。
制造就绪
“他们已经与行业内一些顶级领导者、生态系统中的伙伴建立了合作，现在是他们将其推向更大规模可制造性的时候了，”Ananth 说。“这为新的高性能计算架构规模打开了大门；你不再受二维微缩的限制。”
SRAM 微缩已在约 5 nm 左右结束多年，阻碍了向先进节点的推进。
“如果你能使用后段制程获得远高于边界节点所支持的密度，你就是在推进摩尔定律，”Ananth 说。他称 Kepler 的五位联合创始人是一支独特的团队，拥有物理、材料科学和芯片架构方面的专业知识。五位联合创始人中有三位曾就职于 Intel。
“我想，我是他们雇来找下一个晶体管的第一位工程师，”Manipatruni 说，他曾在 Intel 从事下一代逻辑工作。“Kepler 是从那项努力中自然产生的，当时我们弄清楚了我们需要解决的具体架构问题和材料问题。我们的架构解决了存储器的互连问题，并将存储容量和带宽提高到远超 HBM 路线图，而且实际上不受 HBM 物理限制的约束。”
两种存储器
Olaosebikan 说，Kepler 开发了两种存储器，模糊了 HBM 和 SRAM 之间的界限。
“实际上，我们可以把其中一种存储器视为 HBM 替代品，另一种可以视为 SRAM 替代品，”他补充道。“我们的存储器容量总是会比 SRAM 大得多，至少 10 倍。每瓦带宽将比 HBM 高 5 到 10 倍。”
该公司拒绝详细说明其铁电存储器。
“我们认为，如果我们的外国对手知道这种材料是什么，并且知道它允许他们绕过 EUV，他们就会趋之若鹜，”Manipatruni 说。“所以，我们对材料规格非常谨慎。在过去大约七年里，我们经历了数千次迭代来发现这种铁电材料；成分、梯度、电极，以及发现这类材料所需的一切。”
Kepler 的 HBM 替代品将依赖公司开发的 3D 封装技术。
“当人们做 3D 集成时，他们担心热问题，”Kepler 联合创始人 Rajeev Dokania 说。“我们的 3D 架构绕开了这个问题。相对于传统做法，热开销可以忽略不计。这以非常低的能量成本带来了巨大的带宽。”
该公司表示，其 2027 年的全部产能已分配。Kepler 拒绝透露除 GlobalFoundries 之外的客户和合作伙伴名称，仅表示他们涉及 AI 数据中心以及制造业。从更长期来看，Kepler 还计划开发逻辑芯片。
另见：
动态 AI 需求推动存储多样化
AI 触发新的存储超级周期
大规模存储囤积
AI 与大数据、HBM、存储器、SRAM
INTEL CAPITAL、KEPLER COMPUTING
Kepler Computing, founded in 2018, aims to start production of memories that address HBM and SRAM “bottlenecks” in AI chips by next year, company executives told EE Times. The company is ready to work with industry partners to enter large-scale manufacturing, according to Intel Capital, an investor in Kepler.
The company, which has partnered with GlobalFoundries for production, has built its own fab to ramp up its proprietary 3D and ferroelectric memory technology. The company believes a small Kepler fablet beside a customer’s legacy fab can help leapfrog to leading nodes by multiple generations at one tenth of the investment compared to a new advanced node.
Kepler said it expects to make AI chips with partners such as GlobalFoundries without depending on EUV to reach advanced nodes.
“We look just like Micron, or SK Hynix, or Samsung,” Kepler CEO Debo Olaosebikan told EE Times. “Customers just buy a memory module from us, and then they integrate it with their chip.”
By MRPeasy 10.01.2026
By Francesca Pinto, SPEA Electronic Test Products Copywriter 10.01.2026
By Dr. Jim Shiely, Technical and strategic advisor, Siemens EDA 09.30.2026
AI models are straining conventional memory architectures. Those stresses appear in rising DRAM and HBM design and manufacturing costs, higher energy use and heat dissipation, and diminishing scalability options. AI data centers are also stressing power grids. Most of the energy consumed in an AI facility is spent in data fetches between GPUs and HBM.
Kepler co-founders Amrita Sasi Debo Rajeev and Ramesh
Monolithic stacking
Olaosebikan said the company has achieved monolithic stacking of devices within a chip that avoids thermal problems.
“That’s why we can avoid EUV,” he said. “I can take the old big transistor but just use fewer of them and put things on top of that transistor.”
The transistor on the bottom could be made with EUV.
“We’re okay with that,” Olaosebikan said. “Whatever the base node is, we’re not pushing the requirement that you must shrink that transistor. We are going to amortize the use of that transistor with new devices that we stack on.”
“We increase the memory density by a factor of two to three, and it is actually compatible into CMOS,” Kepler CTO Sasi Manipatruni told EE Times.
The company has reached a stage where it is ready to work with industry partners, Intel Capital managing director Srini Ananth told EE Times.
Manufacturing ready
“They already have partners with some of the top leaders in the industry, in the ecosystem, and the time is now for them to take this into larger scale manufacturability,” Ananth said. “It opens the door to a new scale of high-performance computing architectures; you’re not constrained any longer by two-dimensional scaling.”
SRAM scaling ended years ago around 5 nm, hindering the move to advanced nodes.
“If you can use a backend of line process to get densities that are much higher than what the boundary node supports, you are advancing Moore’s Law,” Ananth said. He called Kepler’s five co-founders a unique team with expertise across physics, material science, and chip architecture. Three of the five co-founders were formerly with Intel.
“I was, I think, the first engineer they hired to go find the next transistor,” said Manipatruni, who worked at Intel on next-generation logic. “Kepler came organically out of that effort when we figured out what is the specific architectural problem and the materials problem that we needed to be addressing. Our architecture addresses the interconnect problem for memory and increases the memory capacity and bandwidth much beyond the HBM roadmap and is not really bound by HBM physics.”
Two memories
Kepler has developed two memories that blur the lines between HBM and SRAM, Olaosebikan said.
“For practical purposes, we can think of one of the memories as an HBM replacement, and the other one can be thought of as an SRAM replacement,” he added. “Our memories are always going to be much larger capacity than you can get with SRAM, at least 10×. There will be 5× to 10× more bandwidth per watt than HBM.”
The company declined to go into detail on its ferroelectric memory.
“We think that if our foreign adversaries know what the material is and know that it allows them to circumvent EUV, they would be all over it,” Manipatruni said. “So, we are being very careful with the materials specifications. Over the past seven years or so, we went through thousands of iterations of discovering the ferroelectric; the composition, the gradients, the electrodes, the whole shebang it takes to discover that class of materials.”
Kepler’s HBM replacement will rely on 3D packaging technology the company has developed.
“When people do 3D integration, they are worried about thermals,” Kepler co-founder Rajeev Dokania said. “Our 3D architecture works around that. There’s negligible thermal overhead relative to the traditional way of doing it. That brings in a tremendous amount of bandwidth at a very low energy cost.”
The company said all its production capacity for 2027 is allocated. Kepler declined to name customers and partners outside of GlobalFoundries, saying only that they are in AI data centers as well as manufacturing. Over the longer term, Kepler also plans to develop logic chips.
Also read:
Dynamic AI Demands Drive Memory Diversity
AI Triggers a New Memory Super Cycle
The Great Memory Stockpile
AI AND BIG DATA, HBM, MEMORY, SRAM
INTEL CAPITAL, KEPLER COMPUTING