三星以3D堆叠HBM瞄准内存极限
三星电子公布了一项克服AI时代内存技术极限的战略，核心是垂直堆叠内存与计算器件的架构。
原文深度解读
本文报道了三星电子在SEMICON Taiwan 2026上公布的CUBE战略，旨在通过垂直堆叠内存与计算器件（如HBM堆叠在GPU上）来克服AI时代的内存技术极限。文章涉及三星高管Choi Jang-seok的演讲，关键时间点为2026年9月1日，关键数字包括HBM5性能翻倍、能效提升20%、热阻降低20%，zHBM性能为HBM4E的8倍、能效3倍、热阻降低75%-90%，zNAND-O位密度为DRAM的10倍、读取带宽和能效为传统NAND的7倍，计划2028年提供样品。文章还提及三星在2026年第二季度DRAM和NAND市场份额分别为39%和29.3%。与电子元器件供应链的关系：三星作为内存和代工巨头，其技术路线影响HBM、NAND等关键元器件的设计、制造和封装，进而影响AI服务器、智能手机等下游供应链。
- 三星电子在SEMICON Taiwan 2026上发布CUBE战略，CUBE代表容量、利用率、带宽和效率。
- 三星计划将HBM垂直堆叠在GPU上，以在不扩大电路板面积的情况下增加内存容量，传统HBM水平放置在GPU周围。
- 三星将调整逻辑芯片和内存的布局以减少数据处理延迟，并利用其在内存和代工业务上的双重优势，下一代HBM5将采用2纳米代工工艺的基底芯片。
- 三星将采用混合铜键合（HCB）和多晶圆键合技术来扩大带宽，应用于下一代zHBM，形成“垂直高速公路”。
- 三星目标：HBM5性能比HBM4E翻倍，能效提升20%，热阻降低20%；zHBM性能为HBM4E的8倍，能效3倍，热阻降低75%-90%。
- 三星开发zNAND-O，采用TSV连接V-NAND芯片，四层或八层垂直堆叠，位密度为DRAM的10倍，读取带宽和能效为传统NAND的7倍，计划2028年提供样品。
供应链影响
- 三星的3D堆叠技术可能改变HBM和GPU的封装方式，影响相关基板、互连材料（如铜键合）和封装设备的供应链需求。
- zHBM和zNAND-O的推出可能取决于三星的2纳米代工产能和良率，进而影响先进制程晶圆代工供应链的分配。
- zNAND-O的TSV垂直堆叠技术可能增加对TSV刻蚀、填充和键合设备的需求，影响半导体设备供应链。
- 三星在DRAM和NAND市场的领先地位可能因技术升级而巩固，可能影响竞争对手（如SK海力士）的市场份额和供应链布局。
- 新技术的量产时间（如zNAND-O 2028年样品）可能取决于客户验证和市场需求，可能影响下游AI设备（如智能手机、PC）的存储方案选择。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
三星电子执行副总裁兼内存业务产品规划负责人崔章硕于9月1日在台北举行的SEMICON Taiwan 2026上展示了公司的CUBE战略。（图片来源：三星电子）
三星电子公布了一项克服人工智能（AI）时代内存技术极限的战略。其核心是一种垂直堆叠内存和计算器件的架构，可在相同占用面积内大幅增加容量，同时缩短数据传输距离。公司正在开发其专有的zHBM和zNAND-O技术，紧随HBM5之后。
三星电子执行副总裁兼内存业务产品规划负责人崔章硕于9月1日在台北举行的SEMICON Taiwan 2026的内存高管峰会上发表了主题演讲，介绍了公司的“CUBE”战略。CUBE代表容量、利用率、带宽和效率。
第一个重点是容量。三星计划将HBM堆叠在图形处理器（GPU）之上，在不扩大电路板面积的情况下增加内存容量。传统HBM水平放置在GPU周围。随着AI模型变得更大并需要更多内存，HBM的安装量以及中介层和封装尺寸也随之增加。“我们现在将垂直扩展，以增加内存容量，而不受印刷电路板（PCB）面积的限制，”崔章硕说。
第二个重点是通过调整逻辑芯片和内存的布局来优化数据处理效率。HBM堆栈底部的逻辑基底芯片处理堆叠DRAM和GPU之间的数据输入、输出和控制。三星计划调整各层的功能和位置，以减少数据处理过程中的延迟。
这种方法利用了三星在内存和代工业务中的双重优势。下一代HBM5将采用2纳米代工工艺制造的基底芯片。“3D不仅仅是堆叠。关键在于每一层如何被利用，”崔章硕说。“三星正在优化逻辑和内存的布局，以消除数据处理延迟。”
三星还将使用混合铜键合（HCB）和多晶圆键合来扩大带宽。HCB直接键合芯片之间的铜互连和绝缘层，无需凸块，从而增加连接密度。多晶圆键合垂直堆叠并键合多个晶圆。芯片之间更短的互连允许更快地传输更多数据。
三星计划将这两种技术应用于其下一代zHBM，从传统的水平连接转向所谓的“垂直高速公路”。“通过大幅缩短芯片之间的距离，我们可以创建一条垂直高速公路，并显著提高带宽，”崔章硕说。
最后一个重点是功耗和热效率。更短的数据传输距离减少了移动数据所需的功耗。这允许在相同功耗下处理更多数据，从而提高每瓦性能。“3D的最终目标是减少移动单个数据位所需的能量，”崔章硕说。“我们正在通过提高结构效率来最大化每瓦性能。”
三星的目标是将HBM5的性能比HBM4E翻倍，同时将每瓦性能提高20%，并将热阻降低20%。它还计划使用热路径块（HPB），这是一种用于将热量从HBM中导出的专用路径。公司还在开发zHBM，目标是实现HBM4E八倍的性能和三倍的每瓦性能，同时将热阻降低75%至90%。
三星还在开发zNAND-O，这是一种下一代NAND闪存产品，其中“O”表示针对设备端环境进行优化。它使用硅通孔（TSV）将V-NAND芯片连接成四层或八层垂直堆叠。该架构旨在增加存储容量和数据加载速度，用于处理智能手机和PC等设备上的大量AI数据。
zNAND-O的位密度是DRAM的10倍，能够提供大型语言模型（LLM）所需的高容量内存。与传统NAND相比，它提供七倍的读取带宽和功耗效率。该技术旨在解决DRAM的容量限制和NAND的速度限制。三星计划于2028年开始提供zNAND-O样品。
三星在第二季度全球DRAM和NAND闪存市场均排名第一。根据Counterpoint Research的数据，三星占据DRAM市场收入的39%，从SK海力士手中夺回榜首，去年第二季度曾失去这一位置。三星在NAND市场也保持第一，市场份额为29.3%。
Choi Jang-seok, executive vice president and head of product planning for Samsung Electronics' Memory Business, presents the company's CUBE strategy at SEMICON Taiwan 2026 in Taipei on Sept. 1. (Photo: Samsung Electronics)
Samsung Electronics unveiled a strategy to overcome memory technology limits in the artificial intelligence (AI) era. At its core is an architecture that vertically stacks memory and computing devices to sharply increase capacity within the same footprint while shortening data-transfer distances. The company is developing its proprietary zHBM and zNAND-O technologies following HBM5.
Choi Jang-seok, executive vice president and head of product planning for Samsung Electronics' Memory Business, presented the company's "CUBE" strategy during a keynote at the Memory Executive Summit at SEMICON Taiwan 2026 in Taipei on Sept. 1. CUBE stands for Capacity, Utilization, Bandwidth and Efficiency.
The first focus is capacity. Samsung plans to stack HBM on top of graphics processing units (GPUs), increasing memory capacity without expanding board area. Conventional HBM is placed horizontally around GPUs. As AI models grow larger and require more memory, the amount of HBM installed has increased along with interposer and package sizes. "We will now expand vertically to increase memory capacity without being constrained by printed circuit board (PCB) area," Choi said.
The second focus is optimizing data-processing efficiency by adjusting the placement of logic dies and memory. The logic base die at the bottom of an HBM stack handles data input, output and control between the stacked DRAM and GPU. Samsung plans to adjust the functions and placement of individual layers to reduce latency during data processing.
The approach takes advantage of Samsung's presence in both memory and foundry businesses. The next-generation HBM5 will use a base die manufactured on a 2-nanometer foundry process. "3D is not simply about stacking. The key is how each layer is utilized," Choi said. "Samsung is optimizing the placement of logic and memory to eliminate data-processing latency."
Samsung will also use hybrid copper bonding (HCB) and multi-wafer bonding to expand bandwidth. HCB directly bonds copper interconnects and insulating layers between dies without bumps, increasing connection density. Multi-wafer bonding vertically stacks and bonds multiple wafers. Shorter interconnects between chips allow more data to be transferred faster.
Samsung plans to apply the two technologies to its next-generation zHBM, shifting from conventional horizontal connections to what it calls a "vertical highway." "By dramatically shortening the distance between dies, we can create a vertical highway and significantly improve bandwidth," Choi said.
The final focus is power and thermal efficiency. Shorter data-transfer distances reduce the power needed to move data. That allows more data to be processed with the same amount of power, improving performance per watt. "The ultimate goal of 3D is to reduce the energy required to move a single bit of data," Choi said. "We are maximizing performance per watt by improving structural efficiency."
Samsung aims to double HBM5 performance from HBM4E while improving performance per watt by 20% and reducing thermal resistance by 20%. It also plans to use a Heat Path Block (HPB), a dedicated path for transferring heat out of HBM. The company is also developing zHBM, targeting eight times the performance and three times the performance per watt of HBM4E while reducing thermal resistance by 75% to 90%.
Samsung is also developing zNAND-O, a next-generation NAND flash product, with the "O" indicating optimization for on-device environments. It uses through-silicon vias (TSVs) to connect V-NAND dies in four- or eight-layer vertical stacks. The architecture is designed to increase both storage capacity and data-loading speeds for handling large volumes of AI data on devices such as smartphones and PCs.
zNAND-O has 10 times the bit density of DRAM, enabling high-capacity memory needed for large language models (LLMs). Compared with conventional NAND, it offers seven times the read bandwidth and power efficiency. The technology is designed to address DRAM's capacity limitations and NAND's speed constraints. Samsung plans to begin offering zNAND-O samples in 2028.
Samsung ranked first globally in both DRAM and NAND flash in the second quarter. According to Counterpoint Research, Samsung held 39% of the DRAM market by revenue, reclaiming the top spot from SK hynix after losing it in the second quarter of last year. Samsung also remained No. 1 in NAND with a 29.3% market share.