EE Times原文发布 08-06 05:35Radar 收录 08-06 06:01查看原文 ↗

三星布局AI内存路线图

Samsung Lays Out AI Memory Roadmap

中文摘要

三星电子公布AI内存技术路线图，押注zHBM与zNAND-O，宣称可突破AI内存墙，实现HBM5性能8倍提升及3D堆叠。该消息来自EE Times报道。

原文深度解读

本文报道三星电子在2026年未来内存与存储峰会（FMS）前夕公布其AI内存技术路线图，旨在突破AI工作负载带来的“数字内存墙”。三星高管Leno Park介绍了基于3D架构、与AI加速器更紧密集成以及工艺和封装进步的多代内存路线图，包括HBM4E、HBM5、zHBM和zNAND-O等关键技术。文章涉及时间节点（2026年、2030年）、关键数字（1000 tokens/s/user、HBM5性能8倍提升、V-NAND 400+层等），与电子元器件供应链中DRAM和NAND闪存的技术演进及AI基础设施需求密切相关。

三星预计到2030年每用户每秒需要1000个token，而2026年约为100个token，需求增长10倍。
HBM4E已进入样品阶段，主要生态系统合作伙伴正在评估，预计2030年HBM将占DRAM销售额的50%以上。
三星HBM设计采用4nm基底芯片，内部TSV数量增加约4倍，先进封装包含超过30万个微凸点，并采用更小的连接间距。
HBM5将采用基于GAA晶体管技术的2nm基底芯片，并缩短中介层通道长度以改善I/O信号。
三星推出zHBM概念，将AI加速器直接置于HBM堆栈之上，形成真正的3D结构，声称下一代接口可实现约8倍于HBM5的性能、10倍以上的内存密度、3倍的能效和不到一半的热阻。
三星第10代TLC V-NAND将拥有超过400层，横向缩小11%，内存密度增加约58%；三星认为2029年后需要突破性技术来克服数字内存墙。

供应链影响

HBM4E的样品阶段和HBM5的规划可能影响DRAM供应链中先进封装和TSV工艺的产能分配，具体取决于客户认证和量产时间。
zHBM和zNAND-O等新架构可能需要与AI加速器厂商紧密协同设计，可能改变内存与逻辑芯片的供应链协作模式。
HBM占DRAM销售额比例预计到2030年超过50%，可能促使DRAM制造商调整产品组合和投资方向，但实际取决于市场需求。
V-NAND层数增加和密度提升可能影响NAND闪存供应链的制造设备和材料需求，但具体影响取决于技术良率和成本。
热管理创新（如热管块）可能引入新的散热组件供应链需求，但取决于技术成熟度和市场接受度。

系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。

正文内容 · AI翻译

中文英文

三星公布多管齐下的方法，以攻克其所谓的由AI工作负载造成的数字内存墙，并概述了包括高带宽内存（HBM）和NAND闪存进展在内的3D内存路线图。

在本周未来内存与存储峰会（Future of Memory and Storage Summit）公开主题演讲前的预简报中，三星电子闪存解决方案副总裁Leno Park阐述了公司围绕3D架构、与AI加速器更紧密集成以及一系列工艺和封装进展构建的多代内存路线图。他表示，该路线图旨在跟上公司预计到本十年末将需要10倍token吞吐量的工作负载。

Park表示，当前的AI基础设施已经难以支持2026年每用户每秒约100个token，但三星正在为更陡峭的曲线做规划。“到2030年，我们预计每用户每秒1000个token，”他声称。

迈向全3D HBM

HBM4E成为三星AI战略的核心并不令人意外，该战略还包括新的冷却技术和向真正3D堆叠的转变。

作者：Piyush Sancheti，中央工程解决方案（3D IC）副总裁，以及Todd Burkholder，3D IC技术撰稿人，Siemens EDA 08.05.2026

作者：Alessandro Chimera，行业解决方案负责人，Spotfire 08.05.2026

作者：MRPeasy 08.01.2026

Park表示，HBM4E目前处于样品阶段，主要生态系统合作伙伴正在评估这些器件。Park将该产品描述为在特别紧凑的开发时间线中的重要一步。“HBM开发周期非常非常快，比以往任何时候都加速了，”他说，并补充说，预计到2030年，HBM将占DRAM销售额的50%以上。

Park表示，三星的HBM设计采用4纳米基底芯片，内部硅通孔（TSV）数量增加约4倍，并采用先进封装，包含超过30万个微凸点和更小的连接间距，以提高可靠性和热管理。

他说，三星正通过采用基于全环绕栅极（GAA）晶体管技术的2纳米基底芯片，并缩短中介层通道长度以改善基底芯片与加速器之间的I/O信号，目标是实现HBM5的又一次代际飞跃。

三星还推出了一种新的热机制，称为热管块（heat pipe block），Park将其描述为HBM堆栈热点上方的“烟囱”，有助于更有效地散热并冷却HBM。

公司还利用FMS机会推出了zHBM，这一概念从当前的2.5D并排布局转变。“我们将把加速器放在HBM堆栈之上，作为一个单一结构，作为一个真正的3D域，”Park说。

通过将AI加速器直接放置在HBM堆栈之上而不是旁边，处理器与内存之间数据传输的距离得以缩短。这种架构预计将提高带宽和能效，同时减少热限制。

三星声称，采用zHBM的下一代接口可实现约8倍于HBM5的性能、10倍以上的内存密度、3倍的能效以及不到一半的热阻。Park表示，实现这些收益需要与加速器合作伙伴紧密协同设计。

zNAND-O瞄准边缘AI瓶颈

HBM本质上是堆叠的同步DRAM，并非三星用来克服数字内存墙的唯一技术。

公司的zHBM公告还辅以zNAND-O，这是一种面向边缘AI和其他数据密集型环境的下一代NAND概念。该架构基于三星的V-NAND技术，旨在通过缩短处理器与内存之间数据传输的距离，将高空间效率与改进的I/O性能、能效和更低延迟相结合。

Park表示，三星第10代TLC V-NAND将拥有超过400层，横向缩小11%，而内存密度增加约58%。Park表示，AI模型越来越大，传统内存架构将无法跟上——行业正在接近一堵墙，需要设计上的结构性改变，而不是又一次常规的速度提升。“2029年之后，我们需要一些突破性技术来克服数字内存墙，”他说。

三星的AI路线图包括zNAND-O，这是公司面向边缘AI和其他数据密集型环境的下一代NAND概念，基于其V-NAND技术。（来源：三星）

另请阅读：

瑞萨电子通过MRDIMM更新解决内存瓶颈

动态AI需求推动内存多样性

加拿大AI生态系统需要更多紧迫性

AI与大数据，内存

三星

Gary Hilson

Gary Hilson是一位自由撰稿人和编辑，为北美各地的印刷和数字出版物撰写了数千篇文章。他的兴趣领域包括软件、企业和网络技术、研究与教育、可持续交通和社区新闻。他的文章已发表在Network Computing、InformationWeek、Computing Canada、Computer Dealer News、Toronto Business Times、Strategy Magazine和Ottawa Citizen上。

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Samsung unveiled a multi-pronged approach to topple what it calls the digital memory wall created by AI workloads, outlining a 3D memory roadmap that includes advances in both high-bandwidth memory (HBM) and NAND flash.

In a pre-briefing ahead of a public keynote at this week’s Future of Memory and Storage Summit, Leno Park, VP of flash solutions at Samsung Electronics, laid out the company’s multi-generation memory roadmap built around 3D architectures, tighter integration with AI accelerators, and a series of process and packaging advances. He said the roadmap is designed to keep pace with workloads that the company expects will require 10× more token throughput by the end of the decade.

Park said current AI infrastructure is already straining to support roughly 100 tokens per second per user in 2026, but Samsung is planning for a much steeper curve. “By the year 2030, we expect 1,000 tokens per second per user,” he claimed.

Moving toward fully 3D HBM

It should come as no surprise that HBM4E is front and center in Samsung’s AI strategy, which also includes new cooling technology and a move to true 3D stacking.

By Piyush Sancheti, VP Central Engineering Solutions (3D IC), and Todd Burkholder, 3D IC Technology Writer, Siemens EDA 08.05.2026

By Alessandro Chimera, Industry Solutions Lead, Spotfire 08.05.2026

By MRPeasy 08.01.2026

Park said HBM4E is now in the sampling phase, with major ecosystem partners evaluating the devices. Park described the product as an important step in an especially compressed development timeline. “The HBM development cycle is really, really fast and [has] accelerated more than ever,” he said, adding that HBM is expected to account for more than 50% of DRAM sales in 2030.

Park said Samsung’s HBM design uses a 4‑nm base die, increases the number of internal through-silicon vias (TSVs) by about 4×, and employs advanced packaging with more than 300,000 microbumps and smaller joint pitches to improve reliability and thermal management.

He said Samsung is targeting another generational leap with HBM5 by using a 2‑nm base die built on gate-all-around (GAA) transistor technology and shortening interposer channel lengths to improve I/O signaling between the base die and the accelerator.

Samsung is also introducing a new thermal mechanism the company calls a heat pipe block, which Park described as a kind of “chimney” over hot spots in the HBM stack to help dissipate heat more efficiently and cool the HBM.

The company also used FMS as an opportunity to introduce zHBM, a concept that moves from the current 2.5D side‑by‑side layout. “We are going to put them into [the] accelerator over to the HBM stack as a single kind of a structure, as a true 3D domain zone,” Park said.

By placing the AI accelerator directly over the HBM stack rather than alongside it, the distance data must travel between processor and memory is shortened. This architecture is expected to improve bandwidth and power efficiency while reducing thermal constraints.

Samsung claimed a next‑generation interface incorporating zHBM could deliver roughly 8× the performance of HBM5, more than 10× the memory density, 3× the energy efficiency, and less than half the thermal resistance. Park said realizing those gains will require close co‑design with accelerator partners.

zNAND-O targets edge AI bottlenecks

HBM, which is essentially stacked synchronous DRAM, is not the only technology Samsung is using to overcome the digital memory wall.

The company’s zHBM announcement was complemented by zNAND-O, a next-generation NAND concept aimed at edge AI and other data-intensive environments. Built on Samsung’s V‑NAND technology, the architecture is designed to combine high space efficiency with improved I/O performance, power efficiency, and lower latency by shortening the distance data must travel between processor and memory.

Park said the 10th generation of Samsung’s TLC V-NAND will have more than 400-layer counts and 11% lateral shrink while memory density has increased by approximately 58%. Park said AI models are getting bigger and that the conventional memory architecture won’t be able to keep up—the industry is approaching a wall that will require a structural change in design rather than another routine speed bump. “After 2029, we need some breakthrough technology to overcome digital memory wall,” he said.

Samsung’s AI roadmap includes zNAND-O, the company’s next-generation NAND concept aimed at edge AI and other data-intensive environments, which builds on its V‑NAND technology. (Source: Samsung)