EE Times原文发布 09-30 06:00Radar 收录 09-30 06:31查看原文 ↗

Astera Labs 更新 Leo 控制器，瞄准内存瓶颈

Astera Labs’ Leo Controller Update Targets Memory Constraints

中文摘要

Astera Labs 更新其 Leo 内存控制器，并将其与 Scorpio 交换芯片搭配，把可扩展内存部署到更靠近 AI 加速器的位置，以缓解 AI 计算中的内存约束。

原文深度解读

本文介绍 Astera Labs 更新其 Leo 内存控制器产品线，包括新的 Leo X-Series fabric-attached 内存控制器以及下一代 Leo 2 E-Series 和 P-Series 控制器，并与 Scorpio fabric 交换芯片搭配，将可扩展内存部署到更靠近 AI 加速器的位置，以缓解 AI 计算中的内存约束。文章涉及 Astera Labs 高管 Thad Omura 和 Ahmad Danesh 的表述，提到 DDR5 容量最高 4 TB、复用 DDR4 最高 768 GB、四块 Nvidia H200 GPU 运行 Qwen2.5-32B 多轮代理工作负载时 TTFT 降低 62%、每秒 token 数增加 22% 等关键数字，并提及 DDR5 定价上涨、晶圆供应紧张，以及 CXL 生态中 Xcena、Synopsys、Marvell 的相关动态。与电子元器件供应链的关系在于：AI 驱动的内存需求正在改变 DRAM 产能分配、DDR4 复用和 CXL 内存扩展方案，可能影响内存器件及相关控制芯片的供需格局。

原文将“内存墙”视为快速扩展 AI 部署的最大障碍，并认为将内存移近计算是最优解；Astera Labs 更新 Leo Smart Memory Controller 家族正是针对这一目标。
Leo 2 E-Series 和 P-Series 延续基于 CXL 的 CPU 附加内存扩展与池化策略，支持 DDR5 和复用 DDR4，每控制器最高 4 TB DDR5 容量、最高 768 GB 复用 DDR4，并新增内存测试、遥测、预测性故障分析和自动修复能力，以帮助超大规模运营商重新部署老旧 DIMM。
在四块 Nvidia H200 GPU 运行 Qwen2.5-32B 模型的多轮代理工作负载基准测试中，Astera Labs 报告相比传统基于 CPU-DRAM 的 KV cache 卸载，TTFT 降低 62%，每秒 token 数增加 22%。
原文引述 Ahmad Danesh 称，随着内存制造商优先生产高带宽内存，DDR5 定价大幅上涨，并出现“因 AI 导致的巨大供应紧缩和晶圆供应紧缩”。
Leo X-Series 专为推理工作负载开发，针对 KV cache 数据可能压垮 GPU 高带宽内存的场景；它不通过 CPU 内存路由数据，而是与 Astera Labs 的 Scorpio fabric 交换芯片配合，创建直接附加到 PCIe fabric 的专用内存层。
Scorpio X-Series 320-Lane Smart Fabric Switch 面向大型 AI 集群，通过 GPU 通信单跳降低延迟；Astera Labs 称其硬件加速和网络内计算引擎可将集合操作提升最高 2 倍，Cosmos 软件则增加一层智能。

供应链影响

AI 推理和多轮代理工作负载对内存容量与带宽的需求可能继续推动 CXL 内存扩展和池化方案采用，从而影响内存控制器、交换芯片及相关接口器件的需求结构。
原文提到 DDR5 定价大幅上涨以及晶圆供应紧缩，可能意味着 DRAM 产能向高带宽内存倾斜，进而影响通用 DDR5 和 DDR4 的供应可得性与交期。
Leo 2 对复用 DDR4 的支持以及内存测试、遥测、预测性故障分析和自动修复能力，可能使部分老旧 DIMM 在超大规模数据中心中获得再利用，从而影响 DDR4 的淘汰节奏和二手/复用内存流通。
Scorpio 等 fabric 交换芯片和网络内计算引擎的采用，可能改变 AI 服务器内部互连和内存拓扑，进而影响相关板卡、连接器和电源管理器件的配套需求。
Xcena、Synopsys、Marvell 等厂商在 CXL 和内存基础设施上的动态，可能加剧该细分领域的竞争，并影响 CXL 相关 IP、芯片和模块的供应链布局；具体影响取决于各厂商产品落地和客户采用速度。

系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。

正文内容 · AI翻译

中文英文

内存墙被视为快速扩展 AI 部署的最大障碍，而将内存移近计算被视为该问题的最优解。

Astera Labs 对其 Leo Smart Memory Controller 家族的更新正是为了实现这一目标。该公司新的 Leo X-Series fabric-attached 内存控制器，以及下一代 Leo 2 E-Series 和 P-Series 控制器，旨在随着 LLM 演变为多轮代理系统而优化内存性能。

在接受 EE Times 简报时，Astera Labs 计算连接集团高级副总裁 Thad Omura 表示，在 AI 早期繁荣期，内存是核心基础设施挑战，因为其竞相跟上 GPU 集群的进步。“所有围绕内存的瓶颈都回来了，并驱动着新架构，我们正试图应对内存约束，”他说。

Astera Labs 新的 Leo X-Series fabric-attached 内存控制器，连同其下一代 Leo 2 E-Series 和 P-Series 控制器，满足了为多轮代理系统优化内存性能的需求。（来源：Astera Labs）

Leo 2 E-Series 和 P-Series 延续了 Astera Labs 基于 CXL 的 CPU 附加内存扩展和池化策略。这些器件同时支持 DDR5 和复用 DDR4 内存，每个控制器最高提供 4 TB DDR5 容量，以及最高 768 GB 的再利用 DDR4。该公司还增加了内存测试、遥测、预测性故障分析和自动修复能力，以帮助超大规模运营商重新部署老旧 DIMM。

By IAR by Qt Group 09.25.2026

By Aveek Sarkar, Director, Ecosystem and Alliance Management Division, TSMC 09.24.2026

By Skyeast International Group Limited 09.24.2026

在使用四块 Nvidia H200 GPU 运行 Qwen2.5-32B 模型并执行多轮代理工作负载的基准测试中，Astera Labs 报告称，与传统的基于 CPU-DRAM 的 KV cache 卸载相比，首 token 时间（TTFT）降低了 62%，每秒 token 数增加了 22%。

内存墙并非 AI 采用者面临的唯一压力。在同一场简报中，产品管理副总裁 Ahmad Danesh 表示，随着内存制造商优先生产高带宽内存，DDR5 定价已大幅上涨。“由于 AI，出现了巨大的供应紧缩和晶圆供应紧缩。”

Leo 2 家族中的动态池化和共享功能旨在减少 stranded memory，并允许按需跨服务器分配容量。“扩展后的 Leo 家族将闲置的、stranded 容量转变为 AI 代理实际可用的内存，且运行在运营商已拥有的硬件上，”Omura 说。“这些 stranded DRAM 是行业的下一个 scale-up 资源。”

Leo X-Series 专为推理工作负载开发，在这些工作负载中，键值（KV）缓存数据可能压垮 GPU 高带宽内存。该控制器不通过 CPU 内存路由数据，而是与 Astera Labs 的 Scorpio fabric 交换芯片配合，创建一个直接附加到 PCIe fabric 的专用内存层。

Leo X-Series 与 Astera Labs 的 Scorpio fabric 交换芯片配合，创建一个直接附加到 PCIe fabric 的专用内存层。（来源：Astera Labs）

Scorpio 的作用是优化与 AI 加速器的连接，并提高每瓦性能，这对数据中心运营商而言是日益重要的指标。Astera Labs 今年早些时候宣布了其最新的 Scorpio fabric 交换芯片。在一次简报中，Omura 表示 fabric 是峰值计算与浪费计算之间的区别。

他说，Scorpio X-Series 320-Lane Smart Fabric Switch 反映了公司为机架级 AI 提供专用连接的核心使命。

“一切都以吉瓦来衡量，”Omura 补充道，可扩展性和韧性同样是重要指标，尤其是在推理以前所未有的规模增长之际。

Danesh 表示，最新的 Scorpio 交换芯片在设计时考虑到了大型 AI 集群。它通过为 GPU 通信提供单跳来降低延迟。

Danesh 说，为了以更低功耗实现这种改进的性能，Astera Labs 在芯片内部集成了专用硬件加速引擎。“这些引擎旨在进一步最大化 token 经济性，并获得更好的每瓦性能。”

他说，Astera Labs 的硬件加速和网络内计算引擎可将集合操作提升最高 2 倍。例如，网络内计算引擎将部分计算从加速器上卸载。“我们可以在我们的硅片内部进行计算，”Danesh 说。“你花更少时间发送数据，更多时间用于计算，这最终提高了 GPU 利用率。”

除了 Astera Labs 硅片内部的专用硬件外，该公司的 Cosmos 软件增加了另一层智能。“部署规模如此之大，正是软件真正提供了大量价值，”Danesh 说。

Danesh 表示，硬件和软件的结合反映了 AI 基础设施设计的更广泛转变；互连不再是被动的管道，而是主动的系统组件，塑造着 GPU 利用率、服务质量、韧性以及数据中心电力预算的经济回报。

CXL 已成为释放内存容量以满足 AI 工作负载需求的重要工具。Astera Labs 五年前发布了其 Leo CXL Memory Accelerator Platform，使 CPU 能够访问和管理 CXL 附加的 DRAM 和持久内存，从而更高效地使用集中式内存资源，并允许该访问在不降低性能的情况下扩展。

韩国初创公司 Xcena 也认为优化数据移动是解决内存瓶颈的关键路径，其最近发布的 CXL Type 3 器件结合了最高 2 TB 的 DDR5、SSD 支持的 InfiniteMemory 容量以及超过 1,000 个定制 RISC-V 核心，将计算推入内存。

Synopsys 最新的 CXL 产品也针对受限的内存容量和带宽，同时旨在使该协议更易于采用。与此同时，Marvell 发布了一套内存基础设施产品，旨在帮助超大规模和云客户将内存移近计算点，减少数据瓶颈，并提高推理工作负载的 token 效率。

另请阅读：

Xcena Cuts Data Movement to Address Memory Bottlenecks

Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure

Meta Recycles DDR4 Memory: Can Others Follow?

AI AND BIG DATA, CXL, DATA CENTER, MEMORY

ASTERA LABS

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The memory wall is seen as the biggest hurdle for rapidly scaling AI deployments, and moving memory closer to compute is seen as the optimal solution to the problem.

Astera Labs’ update to its Leo Smart Memory Controller family aims to do exactly that. The company’s new Leo X-Series fabric-attached memory controller, along with the next-generation Leo 2 E-Series and P-Series controllers, is designed to optimize memory performance as LLMs evolve into multi-turn agentic systems.

In a briefing with EE Times, Thad Omura, senior VP of Astera Labs’ compute connectivity group, said memory is the central infrastructure challenge as it races to keep up with the advances in GPU clustering during the early AI boom. “All the bottlenecks around memory are back and driving new architectures, and we’re trying to deal with the memory constraints,” he said.

Astera Labs’ new Leo X-Series fabric-attached memory controller, alongside its next-generation Leo 2 E-Series and P-Series controllers, addresses the need to optimize memory performance for multi-turn agentic systems. (Source: Astera Labs)

The Leo 2 E-Series and P-Series continue Astera Labs’ CXL-based strategy for CPU-attached memory expansion and pooling. The devices support both DDR5 and reused DDR4 memory, offering up to 4 TB of DDR5 capacity per controller and up to 768 GB of repurposed DDR4. The company has also added memory testing, telemetry, predictive failure analysis, and automated repair capabilities to help hyperscalers redeploy aging DIMMs.

By IAR by Qt Group 09.25.2026

By Aveek Sarkar, Director, Ecosystem and Alliance Management Division, TSMC 09.24.2026

By Skyeast International Group Limited 09.24.2026

In benchmark testing using four Nvidia H200 GPUs running the Qwen2.5-32B model with multi-turn agentic workloads, Astera Labs reported a 62% reduction in time-to-first-token (TTFT) and a 22% increase in tokens per second compared with conventional CPU-DRAM-based KV cache offloading.

The memory wall is not the only pressure faced by AI adopters. In the same briefing, Ahmad Danesh, associate VP of product management, said DDR5 pricing has risen sharply as memory manufacturers prioritize high-bandwidth memory production. “There’s this big supply crunch and wafer supply crunch because of AI.”

Dynamic pooling and sharing features in the Leo 2 family are designed to reduce stranded memory and allow capacity to be allocated across servers as needed. “The expanded Leo family turns idle, stranded capacity into memory an AI agent can actually use, on hardware operators already own,” Omura said. “That stranded DRAM is the industry’s next scale-up resource.”

The Leo X-Series was developed specifically for inference workloads in which key-value (KV) cache data can overwhelm GPU high-bandwidth memory. Rather than routing data through CPU memory, the controller works in conjunction with Astera Labs’ Scorpio fabric switches to create a dedicated memory tier attached directly to the PCIe fabric.

The Leo X-Series works in conjunction with Astera Labs’ Scorpio fabric switches to create a dedicated memory tier attached directly to the PCIe fabric. (Source: Astera Labs)

Scorpio’s role is to optimize connectivity to AI accelerators and improve performance per watt, an increasingly important metric for data center operators. Astera Labs announced its latest Scorpio fabric switch earlier this year. In a briefing, Omura said fabric is the difference between peak and wasted compute.

He said the Scorpio X-Series 320-Lane Smart Fabric Switch reflects the company’s core mission of delivering purpose-built connectivity for rack-scale AI.

“Everything is measured in gigawatts,” Omura added, with scalability and resilience being equally important metrics, especially as inference grows at unprecedented scale.

Danesh said the latest Scorpio switch was built with large AI clusters in mind. It reduces latency by having a single hop for GPU communication.

To deliver that improved performance with lower power, Astera Labs has integrated dedicated hardware acceleration engines inside the chip, Danesh said. “Those engines are built to maximize the token economics further and get better performance per watt.”

He said Astera Labs’ hardware-accelerated and in-network compute engines can boost collective operations by up to 2×. For example, the in-network compute engine offloads some calculations off the accelerator. “We can calculate inside of our silicon,” Danesh said. “You’re spending less time sending the data and more time on the compute, which ultimately increases the GPU utilization.”

In addition to dedicated hardware inside Astera Labs’ silicon, the company’s Cosmos software adds another layer of intelligence. “The scale at which things are being deployed, it’s that software that really provides a lot of value,” Danesh said.

Danesh said the combination of hardware and software reflects a broader shift in AI infrastructure design; interconnects are no longer passive plumbing, but active system components that shape GPU utilization, quality of service, resilience, and the economic return on data center power budgets.

CXL has become an essential tool unlocking memory capacity to meet AI workload demands. Astera Labs released its Leo CXL Memory Accelerator Platform five years ago to enable CPUs to access and manage CXL-attached DRAM and persistent memory, making the use of centralized memory resources more efficient and allowing that access to scale up without slowing down performance.

South Korean startup Xcena also sees optimizing data movement as a critical path to address memory bottlenecks with its recently unveiled CXL Type 3 device that combines up to 2 TB of DDR5, SSD-backed InfiniteMemory capacity, and more than 1,000 custom RISC-V cores to push compute into memory.

Synopsys’s latest CXL offerings also address constrained memory capacity and bandwidth, while aiming to make the protocol easier to adopt. Marvell, meanwhile, released a suite of memory infrastructure products that aim to help hyperscale and cloud customers move memory closer to the point of computation, reduce data bottlenecks, and improve token efficiency for inference workloads.