三星与SK海力士在HBM路径上分道扬镳
在Hot Chips 2026会议上，三星电子和SK海力士提出了截然不同的方法来缓解下一代高带宽内存（HBM）的瓶颈。三星专注于使HBM更易于制造，而SK海力士则侧重于其他技术路线。
原文深度解读
本文报道了在Hot Chips 2026会议上，三星电子和SK海力士针对下一代高带宽内存（HBM）瓶颈提出的不同技术路线。三星侧重于将HBM基础芯片（base die）从简单互连组件转变为主动逻辑芯片，并规划了三个阶段（HBM4/HBM4E、先进HBM、zHBM），目标包括提升能效和带宽。SK海力士则聚焦于先进封装和热管理，如MR-MUF和混合键合技术，并介绍了iHBM技术。会议于8月23日在斯坦福大学举行，涉及HBM4、HBM4E、zHBM等关键产品，以及具体数字如三星zHBM能效提升70%、带宽提升230%，SK海力士封装高度降至775微米等。文章与电子元器件供应链相关，因为HBM是AI芯片的关键组件，其技术演进影响DRAM制造、封装测试和先进逻辑工艺的供应链布局。
- 三星电子和SK海力士在Hot Chips 2026会议上提出了不同的HBM发展策略，三星关注基础芯片智能化，SK海力士强调先进封装和热管理。
- 三星计划从HBM4和HBM4E开始，将基础芯片从传统DRAM工艺转向4纳米级逻辑工艺，以提升能效并增加功能。
- 三星的zHBM概念提出取消中介层，直接垂直堆叠计算芯片和DRAM，声称能效提升70%、DRAM带宽提升230%。
- SK海力士的MR-MUF技术已量产，将封装高度降至775微米，芯片厚度减至之前的90%，间隙高度减半。
- SK海力士的混合键合技术可使核心芯片厚度增加24%，TSV间距降至18微米以下，热阻降低35%。
- SK海力士的iHBM技术（5月推出）在芯片间物理层区域放置导热绝缘材料，预计热阻再降约30%。
供应链影响
- 三星转向4纳米逻辑工艺制造基础芯片，可能影响先进逻辑代工产能的分配，取决于其内部或外部代工合作。
- SK海力士的先进封装技术（如MR-MUF和混合键合）可能增加对封装设备和材料的需求，取决于量产进度。
- HBM堆叠层数增加（16层以上）可能提高对TSV、散热材料等供应链环节的要求，取决于技术成熟度。
- 三星的zHBM若实现，可能改变中介层供应链，减少对传统中介层材料的需求，但取决于技术可行性。
- 两家公司的技术路线差异可能导致HBM供应链分化，影响DRAM晶圆、逻辑晶圆和封装测试的协同，取决于客户采用情况。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
三星电子在Hot Chips 2026上的演示幻灯片。来源：三星电子。
三星电子和SK海力士在Hot Chips 2026上提出了截然不同的方法来缓解下一代高带宽内存（HBM）的瓶颈，三星专注于使HBM基础芯片更智能，而SK海力士则强调先进封装和热管理。
两家公司在8月23日于斯坦福大学举行的Hot Chips 2026开幕日的存储技术教程中展示了各自的策略。三星的Sangwook Han发表了“HBM基础芯片：HBM如何利用先进逻辑工艺演进”的演讲，而SK海力士的Jaesik Lee则发表了“高带宽内存的先进封装”演讲。
三星正在追求所谓的基础芯片激活，将HBM堆叠的底层从相对简单的互连组件转变为主动逻辑芯片。与此同时，SK海力士则专注于解决随着HBM堆叠层数增加而产生的散热和翘曲问题的先进封装技术。
HBM由DRAM核心芯片（C-die）堆叠在基础芯片之上组成。三星表示，从HBM4和HBM4E开始，它将把基础芯片从传统的DRAM制造工艺转向4纳米级逻辑工艺。此举旨在提高能效，并为基础芯片内的附加功能创造空间。
在其路线图的第一阶段，三星计划用基于先进逻辑的芯片间接口取代传统的物理层接口，减少面积需求，并将内存控制器移入基础芯片。它还计划增加基于SRAM的修复功能，能够修复多个芯片上的缺陷。
为了解决散热问题，三星引入了热路径块（HPB），据称可将峰值温度降低超过35%。
第二阶段将增加片上系统级别的可靠性功能，包括温度、电压和老化传感器，以及片上自测块。三星还提出了“先进HBM”的概念，包含外部内存直连接口和能够处理数据预处理任务的处理元件。
在第三阶段，即所谓的zHBM，三星提议取消中介层，将计算芯片直接与DRAM堆叠垂直堆叠。使用晶圆对晶圆键合和混合铜键合将缩短输入输出路径，并大幅降低功耗。
三星表示，基础芯片可以从简单的互连层演变为协处理器，重塑AI系统中内存和逻辑的设计方式。该公司表示，zHBM相比传统HBM4E堆叠，能效可提升70%，DRAM带宽可提升230%。
SK海力士专注于16层及以上HBM堆叠的封装技术。HBM使用硅通孔（TSV）在三维架构中将堆叠的核心芯片连接到基础芯片。随着堆叠密度和带宽的提升，热阻和翘曲成为越来越困难的挑战。
SK海力士表示，其大规模回流模塑底部填充（MR-MUF）技术——已投入量产——改善了翘曲控制，并实现了更细的间距和更窄的间隙填充。该公司表示，已将封装高度降至775微米，芯片厚度减至之前的90%，间隙高度减半。
对于下一代，SK海力士强调了混合键合技术。据该公司称，该技术可使核心芯片厚度增加24%，TSV间距降至18微米以下，即使堆叠高度增加，热阻也能降低35%。
SK海力士在Hot Chips 2026上的演示材料。来源：SK海力士。
Lee还讨论了SK海力士的iHBM技术，该技术于5月正式推出。iHBM在热量集中的芯片间物理层区域放置一种高导热但电绝缘的冷却材料，以创建专用热路径。这种局部热点管理方法在目的上与三星的HPB类似，预计可将热阻再降低约30%。
“从长远来看，我们计划追求三维集成，将HBM直接堆叠在加速器之上，”Lee说。“对于HBM4，我们的目标是与HBM3E相比，热阻改善超过14%，能效提升超过40%，带宽超过每秒2太字节，容量高达48GB。”
Samsung Electronics' Hot Chips 2026 presentation slide. Source: Samsung Electronics.
Samsung Electronics and SK hynix laid out sharply different approaches to easing next-generation high-bandwidth memory, or HBM, bottlenecks at Hot Chips 2026, with Samsung focusing on making the HBM base die more intelligent and SK hynix emphasizing advanced packaging and thermal management.
The two companies presented their strategies during the Memory Technology tutorial on the opening day of Hot Chips 2026 at Stanford University on Aug. 23 local time. Samsung's Sangwook Han presented “HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes,” while SK hynix's Jaesik Lee presented “Advanced Packaging for High Bandwidth Memory.”
Samsung is pursuing what it calls the activation of the base die, transforming the bottom layer of an HBM stack from a relatively simple interconnect component into an active logic chip. SK hynix, meanwhile, is focusing on advanced packaging technologies that address heat dissipation and warpage as HBM stacks add more layers.
HBM consists of DRAM core dies, or C-dies, stacked above a base die. Samsung said it is shifting the base die from a conventional DRAM manufacturing process to a 4-nanometer-class logic process beginning with HBM4 and HBM4E. The move is intended to improve power efficiency and create room for additional functions within the base die.
In the first stage of its roadmap, Samsung plans to replace the conventional physical-layer interface with an advanced-logic-based die-to-die interface, reducing area requirements and moving the memory controller into the base die. It also plans to add an SRAM-based repair function capable of repairing defects across multiple dies.
To address heat, Samsung introduced a Heat Path Block, or HPB, which it said can cut peak temperature by more than 35%.
The second stage would add system-on-chip-level reliability functions, including temperature, voltage and aging sensors, as well as on-chip self-test blocks. Samsung also presented the concept of “advanced HBM,” incorporating an external-memory direct-connect interface and processing elements capable of handling data preprocessing tasks.
In the third stage, known as zHBM, Samsung proposes eliminating the interposer and vertically stacking the compute chip directly with DRAM stacks. Using wafer-on-wafer bonding and hybrid copper bonding would shorten input-output paths and substantially reduce power consumption.
Samsung said the base die could evolve from a simple interconnect layer into a coprocessor, reshaping how memory and logic are designed for AI systems. The company has said zHBM could deliver 70% greater power efficiency and 230% higher DRAM bandwidth than a conventional HBM4E stack.
SK hynix focused on packaging technology for HBM stacks of 16 layers or more. HBM uses through-silicon vias, or TSVs, to connect stacked core dies to the base die in a three-dimensional architecture. As stacking density and bandwidth rise, thermal resistance and warpage become increasingly difficult challenges.
SK hynix said its mass-reflow molded underfill, or MR-MUF, technology—already in mass production—improves warpage control and enables finer pitches and narrower gap filling. The company said it has reduced package height to 775 micrometers, cut chip thickness to 90% of the previous level and lowered gap height by half.
For the next generation, SK hynix highlighted hybrid bonding. The technology could allow core dies to be made 24% thicker, reduce TSV pitch to below 18 micrometers and lower thermal resistance by 35% even as stack heights increase, according to the company.
SK hynix's Hot Chips 2026 presentation material. Source: SK hynix.
Lee also discussed SK hynix's iHBM technology, formally introduced in May. iHBM places a highly thermally conductive but electrically insulating cooling material in the die-to-die physical-layer area, where heat is concentrated, to create a dedicated heat path. The localized hotspot-management approach is similar in purpose to Samsung's HPB and is expected to reduce thermal resistance by roughly another 30%.
“Over the longer term, we plan to pursue three-dimensional integration that stacks HBM directly on top of accelerators,” Lee said. “For HBM4, we are targeting more than a 14% improvement in thermal resistance, over 40% better power efficiency, bandwidth above 2 terabytes per second and capacity of up to 48 GB, compared with HBM3E.”