Intel将High-NA EUV投入量产，但拼接技术仍待验证

Intel Foundry has moved ASML’s high numerical aperture (High-NA) EUV lithography into production, but the harder problem of stitching together larger chip designs is still working its way toward high-volume manufacturing.

Intel said High NA has now been used on more than one million wafers across tool certification, R&D, and production, including select layers of a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake. The company said overlay, throughput, and availability are meeting expectations, while the High-NA-patterned Intel 18A layers deliver yield, defectivity, electrical performance, and reliability comparable with layers patterned using conventional 0.33-NA EUV.

But Panther Lake does not prove that the industry has solved the most difficult stitching problems. The layers patterned with High NA were deliberately selected so that no electrical connections needed to cross the boundary between the two half-fields. The goal was to demonstrate that High NA could operate inside a real production flow and to gain manufacturing experience without changing the performance of the finished product.

That distinction matters because the basic optics of High NA create a new field-size problem.

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Why High NA needs stitching

Conventional 0.33-NA EUV can expose a 26 mm × 33 mm field using a standard 6×6-inch mask. High NA increases the numerical aperture to 0.55, improving resolution, but its anamorphic optics cut the exposure field in half, to 26 mm × 16.5 mm. Designs that fit inside that half-field pose no problem. Larger designs require either two exposures that are stitched together or, eventually, a larger mask.

Image from Intel Mask Operations GM Frank Abboud’s 2025 eBeam Initiative presentation showing the current and future mask options on 6-inch and 6×12-inch masks for use on High NA and low NA EUV tools (Source: Intel Foundry)

The problem is becoming more important as advanced chips get larger. “The need for stitching has only grown,” Chris Mack, co-founder and CTO of Fractilia, a lithography metrology software company, told EE Times. AI accelerators and other large chips are increasingly filling a conventional reticle field, he said, making full-field High-NA patterning more desirable.

Intel Foundry is pursuing several ways to make that possible. The simplest case is to avoid electrically significant crossings at the seam altogether, as Intel did on Panther Lake. A more flexible approach is block-and-route stitching, in which designers place the seam so that critical standard-cell circuitry does not cross it and route connections through higher metal layers instead.

Chris Mack

Mark Phillips, distinguished engineer at Intel Foundry, described block-and-route as one step in a broader strategy for using today’s 6-inch masks with High NA. Intel is also developing what it calls two-dimensional, or “Zipzag,” stitching, in which the seam can move around sensitive circuitry or IP blocks instead of running in a straight line.

The name evokes the zigzag stitch used in sewing. Rather than forcing the boundary between the two High-NA exposures to follow a straight line across the die, Zipzag allows the seam to jog around sensitive regions of the design. That gives chip designers more freedom to keep critical circuitry away from the stitching boundary, although it also adds complexity to mask construction, inspection, and manufacturing control.

Electrical proof comes in stages

Intel has already electrically verified block-and-route on a full-loop test chip with a straight-line seam. The test structures compare the resistance and variation of metal lines crossing the stitching boundary with control structures that don’t cross it, while additional chains and combs check for shorts and opens.

The latest Zipzag test chip goes further. It includes electrical test structures spanning a jogged seam. Inline imaging, overlay, and defect measurements indicate that the jogged regions are healthy, but electrical test results are still pending.

Mack sees block-and-route as relatively low risk. “It seems relatively straightforward, it seems low risk, and it looks like that is the path that everyone will try for their first stitching exercises,” he said.

The harder case is feature stitching, where critical features themselves cross the boundary between two exposures. That requires much tighter control over how the two patterns overlap.

“What we’re talking about is making the technology ready for high-volume manufacturing,” Mack said. At that point, the problem becomes more than just overlay. Dose, focus, edge placement, and stochastic variation all matter.

The seam has to survive statistical tails

Mack said stitching errors of interest can be only a few nanometers, while stochastic edge roughness can also be on the order of a few nanometers. Manufacturers therefore have to distinguish systematic errors caused by stitching from random variation already present in the lithography process.

That challenge is compounded by metrology itself. Scanning electron microscopes, the workhorse for measuring these features, introduce image noise that can resemble real stochastic variation on the wafer. Fractilia is working with Intel on methods to separate those effects and measure systematic stitching errors.

Average results alone may not be enough. Mack said rare failures in the long tails of statistical distributions can emerge at parts-per-million or even parts-per-billion levels. A stitching process that looks healthy on average can therefore still create yield problems once millions of devices are being manufactured.

That’s why yield ultimately matters more than a clean demonstration. “Yield is the big unknown until you actually run the experiments,” Mack said.

The same uncertainty complicates the economic comparison between High NA and continued multi-patterning with 0.33-NA EUV. Engineers can model the cost of one High-NA exposure against two, three, or four lower-NA exposures, but the calculation can change substantially if one approach produces better yield.

Intel’s Panther Lake experiment was not intended to demonstrate such an economic advantage. The High-NA step replaced a 0.33-NA step in a way designed to leave the finished product unchanged. The exercise was primarily about production readiness and learning how the tools behave under real manufacturing loads.

Larger masks could remove the seam

Stitching may eventually become unnecessary. Intel and ASML are pushing the industry toward larger 6×12-inch masks. A mask twice as large in one dimension would allow a High-NA scanner to expose a full conventional reticle field without stitching. Intel said the larger format could also improve productivity on 0.33-NA EUV tools by combining what would otherwise require two 6-inch masks.

Mack said he believes stitching will work, but ultimately, he sees the larger mask as the preferable solution. “The productivity improvements that come from using a 6×12 mask alone will justify its use,” he said.

The transition will not happen quickly. Based on discussions at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference in Monterey in early September, Mack said the industry appears to be coalescing around the larger-mask direction, but he heard timelines of roughly five years to first mask demonstrations and seven years before those masks could be used to print wafers.

Image from Intel Foundry Principal Engineer Kimberly Pierce’s recent SPIE presentation showing a conceptual chip layout where active connections need to cross the boundary between two High NA reticle fields. The pink line indicates Zipzag stitching, allowing designers flexibility to jog the stitch location around specific circuits. (Source: Intel Foundry)

That leaves stitching with an important role for years to come. Intel has demonstrated that High NA itself can operate in production. The next challenge is making stitching sufficiently predictable, measurable, and easy to design around so that customers can use the smaller High-NA field without compromising yield.

The optics are already in the fab. The harder task now is making everything around them routine.

Also read:

SK Hynix’s Intel Liaisons: What You Need to Know

Molecular Contamination: The Hardware Reality of High-NA EUV

IBM, Lam Research Focus High-NA EUV on Sub-1-nm Nodes

Imec Pushes Quantum Toward Manufacturable Silicon Systems

EUV LITHOGRAPHY, HIGH NA-EUV, SEMICONDUCTORS, SOC

INTEL, INTEL FOUNDRY