EE Times原文发布 07-31 23:48Radar 收录 08-01 00:15

CEA-Leti推进堆叠路线图，AI遭遇内存与功耗瓶颈

CEA-Leti Pushes Stacking Roadmap as AI Runs Into Memory and Power Limits

中文摘要

CEA-Leti推进3D堆叠、芯粒及散热技术路线图，以应对AI面临的内存墙与功耗限制。该机构将封装视为架构层面，布局先进封装与异构集成，相关研发涉及芯片堆叠工艺及功耗管理，与半导体供应链中的封装环节紧密相关。

原文深度解读

本文报道了CEA-Leti在3D集成和芯粒架构方面的技术路线图，旨在应对AI模型带来的内存容量和功耗密度挑战。文章引用了CEA-Leti高级项目项目经理Pascal Vivet的观点，讨论了从HBM向更宽、更慢、更近的内存接口的转变，以及3D堆叠、混合键合、背面供电、散热和早期系统协同优化等关键技术。文章与电子元器件供应链中的先进封装、异构集成和芯粒生态紧密相关，涉及封装技术、散热方案和设计方法学。

CEA-Leti的Pascal Vivet表示，3D技术是关键，允许行业在水平、垂直方向扩展，并在开放生态系统中组装最佳芯粒分区技术。
AI模型的主要挑战是计算模型和内存的规模，目标是在未来几年内实现数百GB甚至TB级内存靠近计算引擎集成。
Vivet认为HBM带宽不够宽，希望从HBM转向更慢、更宽、更近的内存接口，使用合适的技术。
CEA-Leti正在开发3D集成工具箱，包括10微米级到1微米以下的互连、die-to-wafer和wafer-to-wafer混合键合、超密集TSV、扇出晶圆级封装和芯粒集成；已演示1微米间距的D2W混合键合，并目标实现200纳米间距的W2W混合键合。
Vivet指出主要限制不是功率预算本身，而是功率密度；水冷定义了芯片的最大功率密度。
Vivet强调早期系统分区最难，需要在物理架构确定前估算功率、热行为、冷却限制、集成方案和成本；芯粒生态需要UCIe等die-to-die通信标准、DFT标准、测试修复方法和芯粒设计套件。

供应链影响

先进封装和3D集成技术的需求可能增加，对混合键合设备、TSV工艺和芯粒设计工具链的供应链可能产生拉动效应。
散热技术（如水冷）的选型可能影响系统设计，进而影响冷却组件（如冷板、泵）的供应链需求。
芯粒生态的开放可能促进IP和芯粒供应商的多样化，但取决于UCIe等标准的普及和芯粒设计套件的成熟度。
早期协同优化和虚拟原型设计可能改变设计流程，对EDA工具和仿真软件的需求可能增加。
不同应用（数据中心、汽车、航天）对集成方案的需求差异可能影响封装和散热供应链的细分市场。

系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。

正文内容 · AI翻译

中文英文

随着AI模型的增长，硬件设计师面临新的挑战：将更多内存放置在更靠近处理器的地方，以更少的能量移动数据，以及冷却功率密度不断上升的系统。对于CEA-Leti高级项目项目经理Pascal Vivet来说，这一挑战正在将3D集成和基于芯粒的架构从先进封装技术推向AI系统设计的中心。

“3D技术是关键，”Vivet告诉EE Times，因为它允许行业“在水平、垂直方向扩展，并在开放生态系统中组装最佳芯粒分区技术。”

从高带宽到宽带宽

直接驱动因素是AI模型的规模以及支持它们所需的内存容量。Vivet表示，主要挑战“显然是计算模型的规模和内存的大小。”

他说，目标是推动现有技术足够远，以便在未来几年内为具有大量内存尽可能靠近计算引擎的系统做好准备。他指的是数百GB甚至可能达到TB级的内存容量集成在芯片附近。

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“为此，3D堆叠将是关键，”Vivet说。

高带宽内存已经成为AI加速器的核心，但Vivet并不认为今天的HBM架构是终点。HBM通过将堆叠DRAM放置在处理器旁边来增加带宽，但连接仍然是并排的。这限制了接口可以变得多宽和多节能。

“HBM意味着高带宽，但还不够宽，”Vivet说。

Leti正在探索的方向不仅仅是传统意义上的更多带宽。而是向物理上更近、更并行的内存接口迈进。未来系统可能不再依赖相邻芯片之间更快的信号链路，而是将内存直接堆叠在计算引擎之上，或使用更密集、更低能量的接口将其放置在附近。

“我们想从HBM转向更慢、更宽、更近的东西，使用正确的技术，”Vivet说。

这对于推理尤其重要，因为推理中的大部分工作负载涉及重复读取模型权重。因此，如果针对读取能量优化的密集内存能够足够靠近计算集成，它们可能发挥重要作用。

Vivet的关注点在于这些内存的位置、它们如何连接到计算，以及由此产生的系统是否能够供电、冷却、测试和制造。

Leti正在开发一个广泛的3D集成工具箱。Vivet表示，该研究所正在研究从10微米级互连到1微米以下的技术，包括die-to-wafer和wafer-to-wafer混合键合、超密集硅通孔、扇出晶圆级封装和芯粒集成。他引用了最近在1微米间距的die-to-wafer混合键合互连演示，以及200纳米的wafer-to-wafer混合键合目标。

1µm间距D2W混合键合测试载体的横截面，在ECTC'2026上展示。（来源：Anthony Zaza | CEA-Leti）

重点不是每个应用都会使用最激进的选择。数据中心AI系统可能需要非常密集的内存上计算集成。汽车、航天和国防应用可能首先受益于芯粒和先进封装，这些技术无需每个模块都构建在同一领先芯片上即可访问先进功能。

堆叠产生功率密度问题

将内存和逻辑堆叠得更近可以减少数据移动能量，但也带来了更困难的热问题。“主要限制不是功率预算本身，而是功率密度，”Vivet说。

这种区别很重要，因为3D集成增加了功能密度。它可以缩短互连并提高带宽，但也集中了热量。现有的冷却技术定义了系统可以承受的最大功率密度。

Vivet以水冷为例。在先进计算农场中，水冷可以比传统风冷提取更多热量，但它仍然定义了一个上限。对于给定面积，冷却方法决定了可以移除多少热能，这反过来限制了芯片中可以耗散多少功率。

“水冷定义了芯片的最大功率密度，”Vivet说。

这使得架构选择与热选择密不可分。数据中心加速器可能能够依赖液冷，而汽车、飞机、无人机或国防平台中的边缘AI系统面临非常不同的热环境。在每种情况下，集成方案必须与应用冷却能力相匹配。

这是Vivet强调更宽更慢接口的原因之一。更低速度下的更多并行通信有助于降低每比特能量并缓解功率密度问题。同样的逻辑适用于电互连，在某些情况下也适用于光子学。

供电也必须重新考虑。随着计算和内存堆叠得更紧密，设计师必须决定功率如何到达计算引擎，以及电源管理功能应该放在哪里。

“电源管理需要很早就重新架构，”Vivet说。

背面供电可能是第一步，但Vivet表示路线图必须更进一步。未来系统可能需要负载点供电、集成无源器件和电源管理功能与计算引擎共同集成，可能作为背面或基于芯粒的功能。

挑战不仅仅是技术性的。它是架构性的。如果供电、冷却和内存放置考虑得太晚，系统可能无法优化。封装不能再被视为已完成芯片的被动容器。

系统级中介层视图，在ISSCC'2026上展示，每个计算芯片配有一个伴随电光路由器，以及两个用于主要IO的额外路由器。（来源：KAM productions）

芯粒需要早期系统协同优化

这种转变导致了Vivet认为路线图中最困难的部分之一。“最困难的是在技术层和功能方面对系统进行早期分区，”他说。

在传统设计流程中，封装决策通常在电路和架构决策之后。在先进AI系统中，这种顺序不再有效。内存容量、互连密度、功率预算、热预算、冷却技术、成本和良率必须在开始时考虑。

在实践中，这意味着在物理架构锁定之前估算功率、热行为、冷却限制、集成方案和成本。

Vivet表示，Leti正在建立早期分析功率和热预算的方法，利用冷却技术和3D集成方案的知识，在完整系统设计之前。成本建模也至关重要，因为最先进的堆叠选项可能不适合每个应用。

虚拟原型设计将变得越来越重要。Vivet表示，未来的架构需要带有技术信息（如密度、功率和热行为）注释的早期软件模型。这些模型可以帮助系统设计师在投入物理实现之前探索功能放置位置。

这也是芯粒生态系统变得关键的地方。对于欧洲来说，芯粒很重要，因为它们可以允许公司共享IP、访问硅片，并组合先进功能、封装技术和特定应用加速器，而无需将每个模块放在同一领先芯片上。

为了使开放的芯粒模型扩展，行业需要的不仅仅是物理集成技术。Vivet指出了die-to-die通信标准（如UCIe）、设计测试标准、测试修复方法和芯粒设计套件，这些允许芯粒更像可重用IP块一样处理。

对于Vivet来说，AI硬件的未来将不仅仅由最快的处理器或最密集的内存决定。它将取决于行业如何智能地堆叠、连接、供电和冷却它们。

结果是先进封装的新角色。它不再仅仅是芯片组装的最后一步。在AI系统中，它正在成为架构本身的一部分。

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CEA-LETI

As AI models grow, hardware designers face a new challenge: placing far more memory closer to processors, moving data with less energy, and cooling systems whose power density keeps rising. For Pascal Vivet, program manager for advanced programs at CEA-Leti, that challenge is pushing 3D integration and chiplet-based architectures from advanced packaging technologies into the center of AI system design.

“3D technology is key,” Vivet told EE Times, because it allows the industry to scale “horizontally, vertically, and to assemble the best technology for chiplet partitioning in an open ecosystem.”

From high bandwidth to wide bandwidth

The immediate driver is the scale of AI models and the memory capacity required to support them. Vivet said the main challenge is “clearly the size of the computing models and the size of memory.”

The goal, he said, is to push available technologies far enough to be ready within the next few years for systems with very large amounts of memory placed as close as possible to the compute engine. He referred to memory capacities in the hundreds of gigabytes and possibly into the terabyte range integrated close to the chip.

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“For that, 3D stacking will be key,” Vivet said.

High-bandwidth memory has already become central to AI accelerators, but Vivet doesn’t see today’s HBM architecture as the end point. HBM increases bandwidth by placing stacked DRAM beside processors, but the connection remains side-by-side. That limits how wide and energy-efficient the interface can become.

“HBM means high bandwidth, but it’s not wide enough,” Vivet said.

The direction Leti is exploring isn’t simply more bandwidth in the conventional sense. It’s a move toward physically closer, more parallel memory interfaces. Instead of relying only on faster signaling links between adjacent dies, future systems could stack memory directly above the compute engine or place it nearby using denser, lower-energy interfaces.

“We want to move from HBM to something slower, wider, closer, using the right technologies,” Vivet said.

This is especially important for inference, where much of the workload involves repeatedly reading model weights. Dense memories optimized for read energy could therefore play a major role if they can be integrated close enough to compute.

Vivet’s focus is where such memories sit, how they connect to compute, and whether the resulting system can be powered, cooled, tested, and manufactured.

Leti is developing a broad 3D integration toolbox. Vivet said the institute is working on technologies ranging from 10-micron-class interconnects to below 1 micron, including die-to-wafer and wafer-to-wafer hybrid bonding, ultra-dense through-silicon vias, fan-out wafer-level packaging, and chiplet integration. He cited a recent demonstration of die-to-wafer hybrid-bonding interconnect at 1-micron pitch and a wafer-to-wafer hybrid-bonding target of 200 nm.

Cross-section of a 1µm-pitch D2W hybrid bonded test vehicle, as presented at ECTC’2026. (Source: Anthony Zaza | CEA-Leti)

The point isn’t that every application will use the most aggressive option. Data-center AI systems may require very dense memory-on-compute integration. Automotive, space, and defense applications may benefit first from chiplets and advanced packaging that provide access to advanced functions without requiring every block to be built on the same leading-edge die.

Stacking creates a power-density problem

Stacking memory and logic closer together can reduce data-movement energy, but it also creates a harder thermal problem. “The main limitation is not the power budget itself, but the power density,” Vivet said.

That distinction matters because 3D integration increases functional density. It can shorten interconnects and improve bandwidth, but it also concentrates heat. Existing cooling technologies define the maximum power density a system can tolerate.

Vivet used water cooling as an example. In advanced computing farms, water cooling can extract more heat than conventional air cooling, but it still defines a ceiling. For a given area, the cooling method determines how much thermal energy can be removed, which in turn limits how much power can be dissipated in the chip.

“Water cooling defines the maximum power density of the chip,” Vivet said.

That makes architectural choices inseparable from thermal choices. A data center accelerator may be able to rely on liquid cooling, while an edge AI system in a car, aircraft, drone, or defense platform faces a very different thermal envelope. In each case, the integration scheme must match the application’s cooling capacity.

This is one reason Vivet emphasizes wider and slower interfaces. More parallel communication at lower speed can help reduce energy per bit and ease the power-density problem. The same logic applies to electrical interconnects and, in some cases, photonics.

Power delivery also must be reconsidered. As compute and memory are stacked more tightly, designers must decide how power reaches the compute engine and where power management functions should sit.

“Power management needs to be re-architected very early,” Vivet said.

Backside power delivery may be a first step, but Vivet said the roadmap must go further. Future systems may require point-of-load power delivery, integrated passives, and power-management functions co-integrated close to the compute engine, potentially as backside or chiplet-based functions.

The challenge isn’t only technical. It’s architectural. If power delivery, cooling, and memory placement are considered too late, the system may be impossible to optimize. The package can no longer be treated as a passive container for completed chips.

A view of the system-on-interposer as presented at ISSCC’2026, with a companion electro-optical router for each computing die and two additional routers for primary IO. (Source: KAM productions)

Chiplets need early system co-optimization

That shift leads to what Vivet sees as one of the hardest parts of the roadmap. “The most difficult is early partitioning of the system in terms of technology layers and functions,” he said.

In conventional design flows, packaging decisions often come after circuit and architecture decisions. In advanced AI systems, that sequence no longer works. Memory capacity, interconnect density, power budget, thermal budget, cooling technology, cost, and yield must be considered at the beginning.

In practice, that means estimating power, thermal behavior, cooling limits, integration scheme, and cost before the physical architecture is locked.

Vivet said Leti is setting up methodologies for early analysis of power and thermal budgets, using knowledge of the cooling technology and 3D integration scheme before the full system is designed. Cost modeling is also essential, because the most advanced stacking option may not be appropriate for every application.

Virtual prototyping will become increasingly important. Vivet said future architectures need early software models annotated with technology information such as density, power, and thermal behavior. Those models could help system designers explore where to place functions before committing to physical implementation.

This is also where chiplet ecosystems become critical. For Europe, chiplets matter because they could allow companies to share IP, access silicon, and combine advanced functions, packaging technologies, and application-specific accelerators without putting every block on the same leading-edge die.

For an open chiplet model to scale, the industry needs more than physical integration technology. Vivet pointed to die-to-die communication standards such as UCIe, design-for-test standards, test-and-repair methods, and chiplet design kits that allow chiplets to be treated more like reusable IP blocks.

For Vivet, the future of AI hardware won’t be determined only by the fastest processor or the densest memory. It will depend on how intelligently the industry stacks, connects, powers, and cools them.

The result is a new role for advanced packaging. It’s no longer simply the last step in chip assembly. In AI systems, it’s becoming part of the architecture itself.