三星推出zHBM原型，将内存直接堆叠在AI加速器上
三星电子发布了下一代3D内存技术，包括z轴高带宽内存（zHBM）和zNAND-O，旨在加强其在快速增长的AI内存市场的地位。zHBM将内存直接堆叠在AI加速器上，以提升带宽和能效。该原型展示了三星在先进封装和内存架构方面的进展，有望应用于AI芯片供应链。
原文深度解读
三星电子在2026年FMS大会上首次展示了下一代3D内存技术，包括zHBM和zNAND-O，旨在加强其在AI内存市场的地位。zHBM将HBM垂直堆叠在AI加速器上，提升带宽和能效；zNAND-O结合V-NAND和TSV技术，面向设备端AI。此外，三星还发布了400层以上的V10 BV-NAND、HBM4E平台、HBM5原型、LPDDR5X-PIM及企业级SSD。这些技术涉及先进封装、内存架构和AI芯片供应链，可能影响高性能计算和AI系统的性能与功耗。
- 三星电子于8月5日在加州FMS 2026大会上首次展示zHBM和zNAND-O原型，8月4日进行主题演讲。
- zHBM将HBM垂直堆叠在AI加速器（xPU）上，沿z轴缩短数据路径，提升带宽和能效。
- 三星称zHBM数据处理性能可达第八代HBM（HBM5）的8倍，每瓦性能提升3倍，热阻降低一半以上。
- zHBM架构允许客户在内存与加速器之间的中间层添加半导体IP块，以扩展容量或优化性能。
- zNAND-O结合V-NAND和TSV技术，采用类似HBF的结构，演示了四层和八层3D封装配置。
- V10 BV-NAND层数超过400层，采用晶圆键合和三层堆叠架构，相比V9密度提升约58%。
供应链影响
- zHBM的定制化IP块设计可能推动AI加速器与内存的协同设计，影响相关IP和封装供应链。
- zNAND-O和V10 BV-NAND的先进封装技术可能增加对TSV和晶圆键合设备的需求。
- 三星作为唯一IDM提供一站式服务，可能影响AI芯片市场的竞争格局和客户选择。
- HBM4E、HBM5等新产品的推出可能影响HBM供应链的产能分配和迭代节奏。
- LPDDR5X-PIM等处理内存技术可能改变数据移动方式，影响相关存储和控制芯片需求。
系统解读，仅作为判断线索，不构成备货、出货、涨价或投资建议。
三星电子DRAM开发副总裁Kim Kyung-ryun介绍zHBM。（来源：三星电子）
三星电子发布了下一代3D内存技术，包括z轴高带宽内存（zHBM）和zNAND-O，该公司寻求加强其在快速增长的人工智能市场中的地位。
三星于8月5日在加利福尼亚举行的未来内存与存储（FMS）2026大会上首次展示了zHBM和zNAND-O的模型。在当地时间8月4日的主题演讲中，该公司还概述了通过使用zHBM、zNAND-O和其他先进内存技术，在高性能计算（HPC）和AI系统中最大化性能和能效的愿景。
zHBM通过新架构提供高达八倍的性能
zHBM模型。（来源：三星电子）
zHBM是一种下一代架构，将HBM沿z轴垂直堆叠在AI加速器（或xPU）之上。该设计最小化了内存与AI处理器之间数据传输的距离，提高了带宽和能效，同时支持大规模AI模型训练和推理所需的超高速数据处理。
传统架构将HBM放置在AI加速器周围。三星表示，这种方法在满足下一代HPC和AI基础设施的性能要求方面面临限制。
据该公司称，zHBM的数据处理性能可达第八代高带宽内存（HBM5）的八倍，同时每瓦性能提升三倍。热阻降低一半以上，增强了系统稳定性和能效。
三星将zHBM描述为可定制的3D内存产品系列。该架构允许客户在内存与AI加速器之间的中间层添加半导体知识产权（IP）块。这些块可以定制，以扩展内存容量或针对特定工作负载优化加速器性能。
该公司表示，计划与客户紧密合作，共同优化AI处理器和内存系统，最大化zHBM的性能潜力。
三星推出类似HBM的zNAND-O和400层以上的V10 BV-NAND
zNAND-O模型。（来源：三星电子）
三星还推出了zNAND-O，这是一个目前正在开发的下一代高性能NAND闪存系列。该技术结合了三星的垂直V-NAND堆叠架构和硅通孔（TSV）技术。TSV用于HBM中，以电气和物理方式连接垂直堆叠的DRAM芯片。三星的zNAND-O采用了类似于高带宽闪存（HBF）的结构，HBF由SK海力士和闪迪开发。
zNAND-O中的“O”指的是设备端AI应用。三星演示了四层和八层3D封装的V-NAND配置，旨在提供高空间效率、更高的读取带宽和更快的响应时间。该公司表示，该技术非常适合需要实时处理大量数据的环境。
在主题演讲中，三星还发布了其V10键合垂直（BV）-NAND技术，层数超过400层。这种下一代NAND架构提高了性能和能效。展示的zNAND-O模型基于V10 NAND平台构建。
BV-NAND将NAND单元阵列和外围电路分离到不同的晶圆上，然后垂直键合在一起。该工艺利用先进的晶圆键合技术，实现多个晶圆的三维集成。
三星进一步将该方法与三层堆叠架构相结合，其中V-NAND单元在三个独立的堆叠中制造，然后垂直互连。该公司表示，与之前的V9代相比，内存密度提高了约58%，在相同占用空间内实现更大的存储容量。读、写和输入/输出性能也得到了增强。
还展示了HBM4E、HBM5和处理内存技术
三星电子在FMS 2026的展位。（来源：三星电子）
三星的展区展示了超过30种内存产品，涵盖DRAM和NAND技术。亮点包括基于HBM4E的下一代AI计算平台、晶圆样品，以及采用热路径块（HPB）技术的HBM5模型。HPB在HBM核心芯片侧面添加垂直散热通道，以改善热管理。
该公司还展示了LPDDR5X-PIM，它将低功耗LPDDR5X DRAM与处理内存（PIM）功能相结合。三星称该产品是全球首款此类实现，能够实现更高效的数据移动和更高的能效。
还展示了针对AI工作负载优化的存储产品，包括PM1763和BM1773。PM1763是三星的下一代企业级固态硬盘（SSD），专为高速读取和高效数据处理而设计。BM1773是一款超高容量企业级SSD，旨在支持大规模AI训练数据集。
三星强调，它仍然是全球唯一一家能够提供涵盖内存、逻辑半导体、代工服务和封装的一站式解决方案的集成设备制造商（IDM）。
“我们可以提供从产品设计阶段到量产的综合服务，帮助客户缩短开发周期，同时优化性能和能效，”该公司表示。“这能够实现根据客户需求定制的AI半导体解决方案。”
Kim Kyung-ryun, Vice President of DRAM Development at Samsung Electronics, introduces zHBM. (Source: Samsung Electronics)
Samsung Electronics unveiled next-generation 3D memory technologies, including z-axis High Bandwidth Memory (zHBM) and zNAND-O, as the company seeks to strengthen its position in the rapidly growing artificial intelligence market.
Samsung on Aug. 5 showcased mockups of zHBM and zNAND-O for the first time at the Future of Memory and Storage (FMS) 2026 conference in California. During a keynote presentation on Aug. 4 local time, the company also outlined its vision for maximizing performance and power efficiency in high-performance computing (HPC) and AI systems through the use of zHBM, zNAND-O and other advanced memory technologies.
zHBM Delivers Up to Eight Times Higher Performance Through New Architecture
zHBM mockup. (Source: Samsung Electronics)
zHBM is a next-generation architecture that vertically stacks HBM on top of AI accelerators, or xPUs, along the z-axis. The design minimizes the distance data must travel between memory and AI processors, improving bandwidth and power efficiency while supporting the ultra-high-speed data processing required for training and inference of large-scale AI models.
Conventional architectures place HBM around the AI accelerator. Samsung said that approach faces limitations in meeting the performance requirements of next-generation HPC and AI infrastructure.
According to the company, zHBM can deliver up to eight times the data-processing performance of eighth-generation High Bandwidth Memory (HBM5) while improving performance per watt by a factor of three. Thermal resistance is reduced by more than half, enhancing both system stability and energy efficiency.
Samsung described zHBM as a customizable family of 3D memory products. The architecture allows customers to add semiconductor intellectual property (IP) blocks to an interlayer positioned between the memory and AI accelerator. These blocks can be tailored to expand memory capacity or optimize accelerator performance for specific workloads.
The company said it plans to work closely with customers to co-optimize AI processors and memory systems and maximize the performance potential of zHBM.
Samsung Reveals HBM-Like zNAND-O and 400-Plus-Layer V10 BV-NAND
zNAND-O mockup. (Source: Samsung Electronics)
Samsung also introduced zNAND-O, a next-generation high-performance NAND flash family currently under development. The technology combines Samsung's vertical V-NAND stacking architecture with Through-Silicon Via (TSV) technology. TSVs are used in HBM to electrically and physically connect vertically stacked DRAM dies. Samsung's zNAND-O adopts a structure similar to High Bandwidth Flash (HBF), which is being developed by SK Hynix and Sandisk.
The "O" in zNAND-O refers to on-device AI applications. Samsung demonstrated four-layer and eight-layer 3D-packaged V-NAND configurations designed to deliver high space efficiency, increased read bandwidth and faster response times. The company said the technology is well suited for environments requiring real-time processing of large volumes of data.
During the keynote, Samsung also unveiled its V10 Bonding Vertical (BV)-NAND technology featuring more than 400 layers. The next-generation NAND architecture improves both performance and power efficiency. The displayed zNAND-O mockup was built using the V10 NAND platform.
BV-NAND separates the NAND cell array and peripheral circuitry onto different wafers before vertically bonding them together. The process utilizes advanced wafer-bonding technology that enables three-dimensional integration of multiple wafers.
Samsung further combines the approach with a three-stack architecture, in which V-NAND cells are manufactured in three separate stacks and then vertically interconnected. The company said memory density improves by approximately 58% compared with the previous V9 generation, enabling greater storage capacity within the same footprint. Read, write and input/output performance have also been enhanced.
HBM4E, HBM5 and Processing-in-Memory Technologies Also Displayed
Samsung Electronics' exhibition booth at FMS 2026. (Source: Samsung Electronics)
Samsung's exhibition area featured more than 30 memory products spanning DRAM and NAND technologies. Highlights included a next-generation AI computing platform based on HBM4E, wafer samples, and an HBM5 mockup incorporating Heat Path Block (HPB) technology. HPB adds vertical heat-dissipation channels along the sides of HBM core dies to improve thermal management.
The company also showcased LPDDR5X-PIM, which combines low-power LPDDR5X DRAM with Processing-in-Memory (PIM) functionality. Samsung described the product as the world's first implementation of its kind, enabling more efficient data movement and improved power efficiency.
Storage products optimized for AI workloads were also displayed, including the PM1763 and BM1773. PM1763 is Samsung's next-generation enterprise solid-state drive (SSD), designed for high-speed reading and efficient data processing. BM1773 is an ultra-high-capacity enterprise SSD aimed at supporting large-scale AI training datasets.
Samsung emphasized that it remains the world's only integrated device manufacturer (IDM) capable of providing a one-stop solution spanning memory, logic semiconductors, foundry services and packaging.
"We can provide integrated services from the product design stage through mass production, helping customers shorten development cycles while optimizing performance and power efficiency," the company said. "This enables customized AI semiconductor solutions tailored to customer requirements."